similar to: [LLVMdev] Instruction Conversion

Rotem Varon wrote: > Hi, > > Let say i am writing a code inside basic block pass and iterating all > the instructions inside, > and i encountered in this instruction : If you're asking how to get the operands of an Instruction, use the getOperand() method: Value * Operand1 = I->getOperand(0); Value * Operand2 = I->getOperand(1); The LLVM doxygen documentation

I'm trying to implement *MUL_LOHI for my processor. My processor has mulxss (e.g.) that gives the 32 high bits of a 64 bit multiply. I tried this in ios2ISelDAGToDAG.cpp: /// Mul/Div with two results case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { SDValue Op1 = Node->getOperand(0); SDValue Op2 = Node->getOperand(1); AddToISelQueue(Op1);

Please test if r115571 has fixed it. Evan On Oct 4, 2010, at 5:00 AM, Heikki Kultala wrote: > Bill Wendling wrote: >> On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: >> >>> Bill Wendling wrote: >>>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >>>> >>>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:

Bill Wendling wrote: > On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > >> Bill Wendling wrote: >>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >>> >>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>>> >>>>> Our architecture has 1-bit boolean predicate registers. >>>>> >>>>> I've

Hi, Let say i am writing a code inside basic block pass and iterating all the instructions inside, and i encountered in this instruction : %3 = add i32 %1, 2 I want to convert this instruction to something like this: add R1, 2, R3 I know the opocode, but i what i need is, the operands %1 and 2 (in this example). I will be grateful if some one will tell me how to do so . -------------- next

I am currently working on DAGToDAGISel class for MIPS and am trying to figure out a way to use INTRINSIC_W_CHAIN for an intrinsic which can return a value. My intrinsic is defined as: Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrReadWriteArgMem]>; i.e. it has four arguments and one return value In DAGToDAGISel when I try to pass it with four arguments and

On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > Bill Wendling wrote: >> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >> >>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>> >>>> Our architecture has 1-bit boolean predicate registers. >>>> >>>> I've defined comparison >>>> >>>> def

Bill Wendling wrote: > On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set

>>Note that the isCommutable flag is only really useful for two-address instructions. If the two inputs are not constrained, nothing is really won by swapping them. Ahh i see, good to know that. >> Does the -view-*-dags output look correct? They do look correct, there are three Xmul_lohi blocks, one returns the low part copied into R14 and the rest of combinations get added and merged

On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > Our architecture has 1-bit boolean predicate registers. > > I've defined comparison > > > def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; > > > > > But then I end up having the following bug: > >

On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > >> Our architecture has 1-bit boolean predicate registers. >> >> I've defined comparison >> >> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;

Hi Chuck, > Most LLVM IR instructions have a result field, according to the Language Reference. > > I want to know, for all LLVM Instructions, is there an easy and consistent way > to know if the current Inst has a result field? > And if yes, what is the best way to obtain it? the instruction is the result! So everywhere you though you needed to use Instruction->getResult(),

Most LLVM IR instructions have a result field, according to the Language Reference. I want to know, for all LLVM Instructions, is there an easy and consistent way to know if the current Inst has a result field? And if yes, what is the best way to obtain it? E.g.: <result> = add<ty> <op1>,<op2> /; yields {ty}:result / All ADD instruction will have a

The instruction mnemonics for the immediate forms of bit-test instructions including bt, btr and bts, btc do not work. llvm-mc barfs with: error: ambiguous instructions require an explicit suffix This is highly user-unfriendly, since we can easily infer what the user meant by inspecting $imm and translating the instruction appropriately. Do it exactly as the Intel manual describes. Note that

The langref says for the 'add' instruction: Syntax: <result> = add <ty> <op1>, <op2> ; yields {ty}:result <result> = nuw add <ty> <op1>, <op2> ; yields {ty}:result <result> = nsw add <ty> <op1>, <op2> ; yields {ty}:result <result> = nuw nsw add <ty> <op1>, <op2> ;

Peter Zotov писал 09.01.2013 19:59: > Hello. > > I've managed to create a bitcode file (attached; also available at > [1]) which produces > a series of identical errors when verified: > > | Global variable initializer type does not match global variable > type! > | %i.NilClass* @nil > > When ran through llvm-dis and recompiled, through, it verifies >

hi, i'm new in R and i need some help. Please, ¿do you know a function how can process cross tables for many variables and show the result in one table who look like this?: +----------------------------------------------------+ |------------------ | X variable | |----------------- | Xop1 | Xop2 | Xop3|.....| +----------------------------------------------------+ |Yvar1 |

Hi all, I have a question with the "getelemptr" instruction. E.g.: I have some GEP instructions in my program. Some look like: <INST_GEP op0=26 op1=64 op2=429/> . <INST_GEP op0=341 op1=64 op2=101 op3=499 op4=0/> The first instruction above in assembly file: %tmp60 = getelementptr [512 x i32]* @weights, i32 0, i32 %k.3.ph Ok, we see it all: Index of @weights in value

On 02/10/2018 06:00 AM, r-help-request at r-project.org wrote: > Did you check the gradient? I don't think so. It's zero, so of course > you end up where you start. > > Try > > data.input= data.frame(state1 = (1:500), state2 = (201:700) ) > err.th.scalar <- function(threshold, data){ > > state1 <- data$state1 > state2 <- data$state2 >

. and yes, one more thing. On some architectures it might be desirable to know the _order_ of instructions in the packet. That is a bit trickier.. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Friday, December 02, 2011 2:40 PM To: LLVM Dev Subject: [LLVMdev]