similar to: [LLVMdev] Question on register class

I am seeing the following assertion in leak detector. /llvm/lib/VMCore/LeakDetector.cpp:43: void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T = void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"' failed. I am creating a list of instructions using BuildMI() and adding them to a basic block using BB->insert(). I am seeing this

Hello, I am writing a MachineFunction pass that converts vector instructions to a sequence of scalar instructions. First, I go through the function and look for vector registers. For each vector register, I create a set of corresponding scalar registers using createVirtualRegister() function and put it in a map. Then I go through the function and replace vector instructions.The basic structure of

On Wed, Jun 3, 2009 at 5:10 PM, Manjunath Kudlur <keveman at gmail.com> wrote: > I am seeing the following assertion in leak detector. > > /llvm/lib/VMCore/LeakDetector.cpp:43: > void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T = > void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"' > failed. > > I am

Hi Bill, I am using the following version of BuildMI : MachineInstrBuilder BuildMI(MachineFunction &MF, const TargetInstrDesc &TID, unsigned DestReg) I do the following : void createInstrs(std::vector<MachineInstr *>& ilist) { Machine Instr *mi; mi = BuildMI(MF, someTID, somereg);

On Wed, Jun 3, 2009 at 12:46 PM, Manjunath Kudlur<keveman at gmail.com> wrote: > Hello, > > I am writing a MachineFunction pass that converts vector instructions > to a sequence of scalar instructions. Why? That really isn't the level you want to be doing that sort of thing normally. Usually, legalization turns illegal vector operations into legal scalar operations. -Eli

I am trying to JIT some code containing an indirect branch (and the corresponding store i8* blockaddress(@label)). I am using LLVM 2.7 code base. I build the ExecutionEngine using EngineBuilder, and call engine->getPointerToFunction(func). When I use setOptLevel(llvm::CodeGenOpt::None), the JITing fails with the following message : JIT.h:131: virtual void*

Dan, Thanks a lot. Using a modifier in the assembly string works for this case. I am trying to solve a related problem. I am trying to print out a set of "mov" ops for the vector_shuffle node. Since the source of the "mov" is from one of the sources to vector_shuffle, depending on the mask, I am not sure what assembly string to emit. For example, if I have d <-

In the X86RegisterInfo.td file, RST is defined like this: // Floating point stack registers (these are not allocatable by the // register allocator - the floating point stackifier is responsible // for transforming FPn allocations to STn registers) def RST : RegisterClass<"X86", [f64], 32, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> { let MethodProtos =

Hi, I am passing a data frame and field name to a function. I've figured out how I can create the formula based on the passed in field name, but I'm struggling to create a vector based in that field. for example if I hard code with the actual field name Y = df$Target, everything works fine. but if I use the passed in parameter name, it doesn't give me what I want, Y = df$mytarget

Hi, I am passing a data frame and field name to a function. I've figured out how I can create the formula based on the passed in field name, but I'm struggling to create a vector based in that field. for example if I hard code with the actual field name Y = df$Target, everything works fine. but if I use the passed in parameter name, it doesn't give me what I want, Y =

Manjunath, I had a very similar problem and I solved it using a custom vector shuffle and addition instead of mov. For example, Vector_shuffle s1, s2, <0,3> is mapped to a custom instruction where I transform the swizzle to a 32bit integer mask and an inverted mask. So I have dst, src0, src1, imm1, imm2 And I have my asm look similar to: Add dst, src0.imm1, src1.imm2 and then in the asm

Hello, I am trying to create a machine instruction for "extractelement". I want to translate r <- extractelement v, 0 to mov r, v.x I was looking at the dag I can use and I found vector_extract. The inputs for this SDnode are a register and a iPtr constant. With that, I need to create 4 separate def's to extract element 0, 1, 2, and 3 and translate to v.x, v.y, v.z, and v.w. I

The target description .td files are allowed to change the default allocation order on a register class by overriding the allocation_order_begin() and allocation_order_end() methods on TargetRegisterClass. Previously, this was used all the time to filter out stack and frame pointers and other reserved registers. I was able to remove most of these custom allocation orders in the tree because the

I want to add a set of "properties" to each instruction in my instruction set, and want to be able to query that in my machine-specific optimizations. My Insts.td file looks as follows : class InstProperty; def propX : InstProperty; def propY : InstProperty; def propZ : InstProperty; class myInst<..., list<InstProperty> props> : Instruction { ... ...

One way to do this is to handle this in the AsmPrinter, with operand modifiers. For example, on x86 there are instructions with ${dst:call} in their asm string. The "call" part is interpreted as an operand modifier. The assembly printer looks for the "call" modifier on MachineOperand::MO_Immediate operands (in X86ATTAsmPrinter::printOperand), which lets it perform custom

Hi! I started writing a LLVM backend for a custom architecture. I have some register and instruction .td files and some other files/classes like a MCStreamer for assembler output. At the moment I can compile some empty programs so far. I implemented the method ::eliminateFrameIndex() similar to the Sparc and ARM backend. The method looks like this: // frame pointer is in reg of class

Christian, Thanks for your reply and the wiki entry. I did search the archives, but evidently I didn't search for the right thing. My bad. Anyways, I am still wondering about the other part of my question. Why aren't there Tablegen backends specific to some architecture backends? Let me describe a different scenario. Suppose my architecture has vector and scalar units, and suppose I want

Manjunath, I asked this question recently, but instead of telling you to search the archive I'm going to take it as a chance to recall how to do it (because I'll do so anyway and even telling tablegen to use an enum for instructions is not as trivial to do as you might think : ) I wrote it up in the wiki at http://wiki.llvm.org/HowTo:_Add_arbitrary_properties_to_instructions Regards,

I am working on implementing a new target for llvm. So far (to make debugging easier), I was compiling a C code into 2 steps: 1) generate the llvm file: clang -ccc-host-triple mytarget -emit-llvm -S myfile.c -o myfile.ll 2) generate the assembly file using llc -march=mytarget myfile.ll Sometimes, I add some verbosity for the 2nd command like "-print-after-all". Now, I'd like to

Hi, Is there a way to see what the default argument llc takes from clang/clang++ ? I'm debugging my backend with a very simple c++ program. Running through *clang++ -target myTarget -S simple.cpp -o simple.s * (bug does no show up) gives me different results from *clang++ -target myTarget -S -emit-llvm -o simple.cpp -o simple.ll* *llc simple.ll -o simple.s *(bug shows up) Just trying to