similar to: [LLVMdev] adjust address calculus for an architecture that does not address bytes

Christian Sayer wrote: > Hi, > my target architecture has a kind of "16bit addressing mode", i.e. one address does not address 8 bit but a 16bit chunk. Consequently, every constant used to calculate effective addresses must be divided by two. > So far this is not such a problem for stack objects since FrameIndexes, function arguments etc. have a lot of custom lowering code where

> > At first I thought this could be handled when lowering > loads and stores, but I realize that I can only catch the > targeted addresses of loads/stores here - however address > calculation nodes may occur anywhere in a DAG. > > > > So my first impulse would be to adjust the constants when > the GEP instructions are transformed to ADDs. Afaics his > would mean

Hi all, I am writing a custom backend. Doing more testing i notice that for some reason something like: int test(int x) { return x - 1; } is being turned into this IR: ; Function Attrs: nounwind define i32 @test(i32 %n) #0 { entry: %n.addr = alloca i32, align 4 store i32 %n, i32* %n.addr, align 4 %0 = load i32* %n.addr, align 4 %sub = sub nsw i32 %0, 1 ret i32 %sub } But finally in

Not paying close attention to detail, I entered the equivalent of pstr<-c("b1=200", "b2=50", "b3=0.3") when what I wanted was pnum<-c(b1=200, b2=50, b3=0.3) There was a list thread in 2010 that shows how to deal with un-named vectors, but the same lapply solution doesn't seem to work here i.e., pnum<-lapply(pstr, as.numeric) or similar vapply

Hi, During instruction selection, I have the following code for certain LOAD instructions: const LoadSDNode *LD = cast<LoadSDNode>(N); SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other, LD->getBasePtr(), LD->getChain()); // Honestly, I have no idea what this does, but other memory // accessing instructions

This is the first part of a pair of patch series which aim to let us use nbdkit_parse_size (or rather, an equivalent common function) in nbdcopy, so we can write: nbdcopy --request-size=32M ... We can't do that now which was annoying me earlier in the week. This commit creates a new function called human_size_parse which is basically nbdkit_parse_size, and turns nbdkit_parse_size into a

See companion patch: Subject: [PATCH nbdkit] server: Move size parsing code (nbdkit_parse_size) to common/include This is the second part of the patch. It adds the new human_size_parse function to libnbd and then uses it for parsing --queue-size, --request-size and --sparse. The main complication here is that there was already a common/utils/human-size.h header which ends up (eventually)

I am trying to prototype a back end for a new processor. It has a 64-bit datapath, so all registers are 64 bits and load instructions always extend to 64 bits. But the type 'int' is 32 bits, and arithmetic instructions have variants that operate on only the lower 32 bits of each register. So for a basic 'a = b + c' example, we get %0 = load i32, i32* @b, align 4, !tbaa !1 %1

On 7/29/2017 1:28 AM, Dr. ERDI Gergo via llvm-dev wrote: > Hi, > > During instruction selection, I have the following code for certain > LOAD instructions: > > const LoadSDNode *LD = cast<LoadSDNode>(N); > SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), > VT, PtrVT, MVT::Other, > LD->getBasePtr(), LD->getChain()); >

Hi, I'd like to define a pseudo-instruction whose expansion will, as a side-effect, overwrite an input register's value: the pseudo-instruction ldw r1:r2, P to load 2 bytes from memory address P is to be expaneded to ld r1, P+ ld r2, P where "ld _, P+" is an instruction that loads a single byte from P, and post-increments P by one. How can I represent this behaviour in

Hi, Im currently dealing with large datasets of some climatic parameters and I'm performing some EOF analysis on them. The problem is that for one of the datasets, the continents are labelled as NA's (since the data was gathered over the oceans). I don't know to which extent the dropping of those NA's from the matrix will affect the future calculus, and how to maintain the

I am trying to know exactly the formulas used to calculate aic for glm models. In glm.fit, the calculus of aic is: aic.model <- aic(y, n,mu, weights, dev) + 2 * fit$rank where 2 * fit$rank is (may be am i wrong?) twice the numbers of parameters p and aic(y, n, mu, weights, dev) refers to the function defined in the family function (which is for Gamma family, for instance) aic

Hello! I have the following simple IR: ================================== @l = common global i64 0, align 8 define void @hello() nounwind { entry: store i64 -4919131755279862989, i64* @l ret void } define i32 @main(i32 %argc, i8** %argv) nounwind { entry: call void @hello() %tmp = load i64* @l %conv = trunc i64 %tmp to i32 ret i32 %conv } ==================================

Hi, I'm doing a backend port and I'm having trouble with adds that have negative immediates. My architecture only has instructions for subtracting and adding 8bit immediate values (they will be zero-extended, thus unsigned). Bigger immediates have to be moved in a register first. The problem is: Expressions like "b - 1" result in "add nsw i32 %b, -1" in LLVM IR. They

Hello, I'm considering creating an LLVM backend for a 16 bit processor and modelling it around the (experimental) MSP430 back end. When reviewing MSP430InstrInfo.td I see def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; and can see in MSP430ISelLowering.cpp that ISD::GlobalAddress: ISD::BlockAddress: ISD::ExternalSymbol all get lowered to

The reason the ones in PPCInstrInfo.td don't have the patterns to match is the reason they are more analogous to your problem. Namely, tblgen does not have a way to produce nodes with more than one result. The load-with-update instructions do exactly that - one of the inputs is also an output, but the other output is independent (and necessarily a separate register). The FMA variants have

Hi, All, I want to add one intrinsic function for my particular backend. Let's say the intrinsic function is named "foo" which takes two i32 inputs and has one i32 output. First, I add this line "def int_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadArgMem]>;" in /include/llvm/IR/Intrinsics.td. Then, in my target/InstrInfo.td, I'm supposed

I've come across a couple errors when building LLVM 2.1 in VC++ 2005. 1) CodeGen/RegisterCoalescer.cpp is not included in the project 2) System/Win32/DynamicLibrary.inc - ELM_Callback is declared with a PSTR ModuleName argument. This causes a compile error - the callback typedef specifies PCSTR. Also, I'd like to suggest adding the following to config.h, to eliminate the spurious

On 25 Jul 2012, at 04:49, Paul Shortis wrote: > Hello, > > I'm considering creating an LLVM backend for a 16 bit processor and > modelling it around the (experimental) MSP430 back end. > > When reviewing MSP430InstrInfo.td I see > > def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; > > and can see in MSP430ISelLowering.cpp

Dear List, I have got error message when I run the R-code. Can anyone has a suggestion? v.code <- df.bm7[,c(10:31)]; v.code[1:3,] names(v.code) CM = v.code # variable binomial code sim.sp <- function(data,CM,n,N) { C <- matrix(rep(NA,N),ncol=1) for(i in 1:N) { j <- n xx <- which(colSums(CM[j,])==1) V <- names(xx) V <- paste(V,