similar to: [LLVMdev] Proposal to disable some of DAG combine optimizations

Displaying 20 results from an estimated 10000 matches similar to: "[LLVMdev] Proposal to disable some of DAG combine optimizations"

2009 Mar 23
3
[LLVMdev] Proposal to disable some of DAG combine optimizations
I can't think of any workaround? this optimization eliminates so much information that if we want to retrieve back, it will take a lot of processing and may not necessarily be able to retrieve the lost information for all cases. Besides, why does the generic part of llvm have to force an optimization that is counter productive to some targets? If there are other phases that do the same
2009 Mar 24
0
[LLVMdev] Proposal to disable some of DAG combine optimizations
The code sequence: > store %tmp1, var > > tmp4 = add %tmp3 , %tmp1 > can happen even if you eliminate the specific dag combine in question. The real solution lies elsewhere. To me, this seems more like a register allocation problem. Evan On Mar 22, 2009, at 9:39 PM, Alireza.Moshtaghi at microchip.com wrote: > I can't think of any workaround? this optimization eliminates
2009 Mar 24
1
[LLVMdev] Proposal to disable some of DAG combine optimizations
Remember, our target does not have registers like ordinary processors do. So register allocation is really not going to do much for us. What we have to do is to exploit the existing opportunities in the source code and try to generate code based on such opportunities. The dag combination in question is one such opportunity that is being destroyed by the optimization. You maybe right in that this
2009 Mar 20
0
[LLVMdev] Proposal to disable some of DAG combine optimizations
Disabling this optimization in the DAG combiner isn't going to eliminate the problem; instcombine, GVN, and maybe even others also happen to perform this optimization. You may find it more effective to look for ways for codegen to recover in these kinds of situations. Dan On Mar 19, 2009, at 10:38 AM, Alireza.Moshtaghi at microchip.com wrote: > Some of the optimizations that the first
2010 Jul 16
3
how to skip a specific value when using apply() function to a matrix?
Hello R experts, I'd like to studentize a matrix (tmp1) by column using apply() function and skip some specific values such as zeros in the example below to tmp2 but not tmp3. I used the script below and only can get a matrix tmp3. Could you please help me to studentize the matrix (tmp1) without changing the zeros and generate a new matrix tmp2? Thanks, Joshua tmp1 [,1] [,2] [,3] [,4]
2012 Feb 01
3
[LLVMdev] Issues with the llvm.stackrestore intrinsic
Hi, I have two problems regarding the llvm.stackrestore intrinsic. I'm running on 3.0, but a quick test on trunk also showed the same behavior. First problem: --------------- I have code like: tmp1 = call llvm.stacksave() tmp2 = alloca [do some stuff with tmp2] call llvm.stackrestore(tmp1) [some other stuff] tmp3 = call llvm.stacksave() tmp4 = alloca [do some stuff
2007 Sep 27
2
[LLVMdev] Lowering operations to 8-bit!
I'm working on version 2.0 The assertion at line 2380 of LegalizeDAG.cpp fails when it is trying to lower the add with i16. assertion reads: assert(MVT::isVector(Node->getValueType(0)) && "Cannot expand this binary operation!"); I am trying to compile a very simple program as follows: short var; void foo(void) { Var++; } The input bytecode, (in addition to the
2010 Sep 10
1
[LLVMdev] Missing Optimization Opportunities
Hi, I'm using LLVM 2.7 right now, and I found "opt -std-compile-opts" has missed some opportunities for optimization: define void @spa.main() readonly { entry: %tmp = load i32* @dst-ip ; <i32> [#uses=3] %tmp1 = and i32 %tmp, -16777216 ; <i32> [#uses=1] %tmp2 = icmp eq i32 %tmp1, 167772160 ; <i1> [#uses=2]
2006 Jul 23
3
RfW 2.3.1: regular expressions to detect pairs of identical word-final character sequences
Dear all I use R for Windows 2.3.1 on a fully updated Windows XP Home SP2 machine and I have two related regular expression problems. platform i386-pc-mingw32 arch i386 os mingw32 system i386, mingw32 status major 2 minor
2007 Sep 28
0
[LLVMdev] Lowering operations to 8-bit!
On Sep 27, 2007, at 4:35 PM, <Alireza.Moshtaghi at microchip.com> <Alireza.Moshtaghi at microchip.com> wrote: > I'm working on version 2.0 > The assertion at line 2380 of LegalizeDAG.cpp fails when it is > trying to > lower the add with i16. > > assertion reads: > assert(MVT::isVector(Node->getValueType(0)) && > "Cannot expand this
2011 Feb 22
2
[LLVMdev] Clone a function and change signature
Hi, I want to clone a given function, and add an argument to it. I then want to add a call to that new function. I have a callInstruction CI, which I want to transform to call this new function, and to take a new argument. The code I added was as follows CI->getCalledFunction()->dump(); Function* DirectF = CloneFunction(CI->getCalledFunction());
2008 May 23
3
[LLVMdev] Troubling promotion of return value to Integer ...
On May 20, 2008, at 2:16 PM, <Alireza.Moshtaghi at microchip.com> <Alireza.Moshtaghi at microchip.com > wrote: > >> Ok, I'm not sure what issue you mean. Can you restate? > > I'm referring to your statement (below) where you say "there needs > to be > some attribute (or something) on foo". Ok. > What I don't understand is I >
2007 Sep 27
3
[LLVMdev] Vector swizzling and write masks code generation
Hey, as some of you may know we're in process of experimenting with LLVM in Gallium3D (Mesa's new driver model), where LLVM would be used both in the software only (by just JIT executing shaders) and hardware (drivers will implement LLVM code-generators) cases. While the software only case is pretty straight forward I just realized I missed something in my initial evaluation. That
2012 Jun 01
2
[LLVMdev] legalization of truncating stores in LegalizeDAG.cpp
In LegalizeDAG.cpp, truncating stores are custom-lowered in line 1314-1317: 1314 case TargetLowering::Custom: 1315 ReplaceNode(SDValue(Node, 0), 1316 TLI.LowerOperation(SDValue(Node, 0), DAG)); 1317 break; Is there a reason it doesn't check whether the SDValue returned from TargetLowering::LowerOperation is null before it replaces the
2013 Oct 27
2
[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?
The following piece of IR is a fixed point for opt -std-compile-opts/-O3: --- target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" ; Function Attrs: nounwind readonly define i32 @get32Bits(i8*
2008 May 28
2
[LLVMdev] Troubling promotion of return value to Integer ...
On May 27, 2008, at 3:33 PM, <Alireza.Moshtaghi at microchip.com> <Alireza.Moshtaghi at microchip.com > wrote: > Chris, > I see, so in deed the front-end sets the attributes on the declaration > of the called function; which in theory is also available to the > caller > through the CALL node. Right. > Now here is what I think: > I agree that 4 attributes are
2013 Aug 22
1
From POSIXct to numeric and back with time zone
From POSIXct to numeric and back with time zone I am running regressions on data which has time series with different time resolution. Some data has hourly resolution, while most has either daily or weekly resolution. Aggregation is used to make the hourly data daily, while liner interpolation is used to find daily data from the weekly time series. This data manipulation requires some careful
2017 Apr 28
3
Store unswitch
Hi Danny, Thanks for that :) However I've just updated the prototype patch to NewGVN and it didn't need any API changes - all I rely on is GVNExpression. Hongbin, I wanted to explain a little about what GVNSink can currently do, what it was designed for and hopefully how to make it handle your testcase. *Background* Common code sinking is more difficult to efficently do than one might
2009 Apr 13
1
[LLVMdev] Porting LLVM backend is no fun yet
Dan Gohman wrote: > There certainly are wishlist items for TableGen and TableGen-based > instruction descriptions, though I don't know of an official list. > Offhand, > a few things that come to mind are the ability to handle nodes with > multiple results, Is there an official workaround, BTW? - Volodya
2008 May 28
0
[LLVMdev] Troubling promotion of return value to Integer ...
Hi Chris, please read below: > In many cases that is true, but for indirect calls (calls through a > function pointer) it isn't. > > > All that is needed is to add some kind of sign attribute to the > > definition of callee function which will be set by the front-end and > > eventually saved in Function class. > > Sure. Adding an attribute is what we need