Displaying 20 results from an estimated 11000 matches similar to: "[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/"
2009 Feb 23
0
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
On Feb 23, 2009, at 1:20 PM, Scott Michel wrote:
> Chris:
>
> I did float this by the dev list first a couple of weeks ago, didn't
> receive any comments.
Ok, I didn't see it, sorry about that.
> It's not entirely gratuitous; the rationale for adding a new node
> class is threefold:
>
> a) Convenience for the backends. Since it benefits multiple backends
2009 Feb 23
2
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
On Mon, Feb 23, 2009 at 1:46 PM, Chris Lattner <clattner at apple.com> wrote:
>
> On Feb 23, 2009, at 1:20 PM, Scott Michel wrote:
>
> Chris:
>>
>> I did float this by the dev list first a couple of weeks ago, didn't
>> receive any comments.
>>
>
> Ok, I didn't see it, sorry about that.
It happens. :-)
> a) Convenience for the
2009 Feb 24
2
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
On Feb 23, 2009, at 6:13 PM, Scott Michel wrote:
> On Mon, Feb 23, 2009 at 4:03 PM, Nate Begeman <natebegeman at me.com>
> wrote:
>
> It's basically as Chris said; there will be a ShuffleVectorSDNode,
> and appropriate helper functions, node profile, and DAGCombiner
> support.
>
> Fine. For vector shuffles. But again, what about vector constants,
>
2009 Feb 24
3
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
On Feb 23, 2009, at 2:49 PM, Scott Michel wrote:
> On Mon, Feb 23, 2009 at 2:19 PM, Nate Begeman <natebegeman at me.com>
> wrote:
>
> On Feb 23, 2009, at 1:46 PM, Chris Lattner wrote:
>
> In my opinion, the proper direction for shuffles is:
>
> 1. Back out your patch.
> 2. Move the functionality of "is splat" etc to method somewhere, e.g.
> on
2009 Feb 23
2
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
On Feb 23, 2009, at 1:46 PM, Chris Lattner wrote:
> In my opinion, the proper direction for shuffles is:
>
> 1. Back out your patch.
> 2. Move the functionality of "is splat" etc to method somewhere, e.g.
> on SDNode.
> 3. Introduce a new ShuffleVectorSDNode that only has two SDValue
> operands (the two input vectors), but that also contains an array of
> ints in
2009 Feb 23
0
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
On Mon, Feb 23, 2009 at 2:19 PM, Nate Begeman <natebegeman at me.com> wrote:
>
> On Feb 23, 2009, at 1:46 PM, Chris Lattner wrote:
>
> In my opinion, the proper direction for shuffles is:
>>
>> 1. Back out your patch.
>> 2. Move the functionality of "is splat" etc to method somewhere, e.g.
>> on SDNode.
>> 3. Introduce a new
2009 Feb 24
0
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
On Mon, Feb 23, 2009 at 8:26 PM, Chris Lattner <clattner at apple.com> wrote:
>
> On Feb 23, 2009, at 6:13 PM, Scott Michel wrote:
>
> On Mon, Feb 23, 2009 at 4:03 PM, Nate Begeman <natebegeman at me.com> wrote:
>
>>
>> It's basically as Chris said; there will be a ShuffleVectorSDNode, and
>> appropriate helper functions, node profile, and
2009 Feb 24
0
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
On Mon, Feb 23, 2009 at 4:03 PM, Nate Begeman <natebegeman at me.com> wrote:
>
> It's basically as Chris said; there will be a ShuffleVectorSDNode, and
> appropriate helper functions, node profile, and DAGCombiner support.
>
Fine. For vector shuffles. But again, what about vector constants, e.g.,
v4i32 <0, 1, 2, 3, 4>? BuildVectorSDNode is still a reasonable subclass
2009 Feb 24
1
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
On Feb 23, 2009, at 10:30 PM, Scott Michel wrote:
> On Mon, Feb 23, 2009 at 8:26 PM, Chris Lattner <clattner at apple.com>
> wrote:
>
> On Feb 23, 2009, at 6:13 PM, Scott Michel wrote:
>
>> On Mon, Feb 23, 2009 at 4:03 PM, Nate Begeman <natebegeman at me.com>
>> wrote:
>>
>> It's basically as Chris said; there will be a
2009 Feb 23
0
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
On Feb 23, 2009, at 2:15 PM, Scott Michel wrote:
> And the first thing the helper method would have to check is if this
> SDNode is a BUILD_VECTOR node, right?
Right. It's really not much different than what you have now, just
moving the point where you check. In your code right now, when you
want to call your isConstantSplat method, you first dyn_cast the node
to a
2009 Feb 24
3
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
> 3. Introduce a new ShuffleVectorSDNode that only has two SDValue
> operands (the two input vectors), but that also contains an array of
> ints in the node (not as operands).
...
> The important part of #3 is that we really want an array of ints
> (using -1 for undef) for the shuffle mask, not "operands". This
> eliminates the nastiness we have now were we
2009 Feb 24
0
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
Duncan:
I'm still stymied how this whole thread ended up about shuffle vector nodes,
when the original problem was my build vector patch. I'm still working on
backing the build vector patch out (it isn't clean with all of the
intervening commits and I have pressing management tasks which command my
attention.)
-scooter
On Tue, Feb 24, 2009 at 12:28 AM, Duncan Sands <baldrick at
2009 Feb 25
3
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
Things are still broken. Unfortunately llvm test suite does not
contain enough vector code to fully test this. Can you revert the
patch first?
Evan
On Feb 24, 2009, at 7:14 PM, Scott Michel wrote:
> Evan:
>
> I did not encounter this back trace before I committed the newest
> BuildVectorSDNode patch, which removed all class instance members
> and passes results back via
2009 Feb 25
0
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
Evan:
I work on reverting it, although, when I tried yesterday, it wasn't
particularly clean (lots of rejected patches, presumably due to intervening
commits.)
Are you still getting the backtrace or is this just a case of incorrectly
generated code?
-scooter
On Wed, Feb 25, 2009 at 10:09 AM, Evan Cheng <echeng at apple.com> wrote:
> Things are still broken. Unfortunately llvm
2009 Feb 24
3
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
I believe this patch has broken a PPC app that I am tracking. Here is
a reduced test case. Reproduce with llc -mattr=+Altivec -mcpu=g5. The
backtrace looks like this:
#0 0x9333ae42 in __kill ()
#1 0x9333ae34 in kill$UNIX2003 ()
#2 0x933ad23a in raise ()
#3 0x933b9679 in abort ()
#4 0x933ae3db in __assert_rtn ()
#5 0x0008bd8f in llvm::MVT::getVectorElementType (this=0xbfffdda4) at
2009 Mar 02
1
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
Scott,
In case you missed it, I reimplemented your
BuildVectorSDNode::isConstantSplat method following the suggestions
from Chris. The revised version passes "make check" for llvm.
Assuming that it also passes Evan's tests, I think it should also do
what you need for CellSPU.
On Feb 25, 2009, at 12:16 PM, Scott Michel wrote:
> Evan:
>
> I work on reverting it,
2009 Feb 25
0
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
Evan:
I did not encounter this back trace before I committed the newest
BuildVectorSDNode patch, which removed all class instance members and passes
results back via reference parameters.
-scooter
On Tue, Feb 24, 2009 at 11:39 AM, Evan Cheng <evan.cheng at apple.com> wrote:
> I believe this patch has broken a PPC app that I am tracking. Here is a
> reduced test case. Reproduce
2011 Mar 17
2
[LLVMdev] Long-Term ISel Design
Chris Lattner <clattner at apple.com> writes:
>> 1. We have special target-specific operators for certain shuffles in X86,
>> such as X86unpckl.
> It also eliminates a lot of fragility. Before doing this, X86
> legalize would have to be very careful to specifically form shuffles
> that it knew isel would turn into (e.g.) unpck operations. Now
> instead of
2011 Mar 18
0
[LLVMdev] Long-Term ISel Design
On Mar 17, 2011, at 9:32 AM, David A. Greene wrote:
> Chris Lattner <clattner at apple.com> writes:
>>> 1. We have special target-specific operators for certain shuffles in X86,
>>> such as X86unpckl.
>
>> It also eliminates a lot of fragility. Before doing this, X86
>> legalize would have to be very careful to specifically form shuffles
>> that
2019 Aug 29
6
[SVE][AArch64] Codegen for a scalable vector splat
Hi,
During the discussion on introducing scalable vectors we established that we could use the canonical IR form for splats of scalable vector types (insert element into lane 0 of an undef vector, shuffle that with another undef vector of the same type and a zeroinitializer mask).
We do run into a problem for lowering to SelectionDAG however, since the canonical form there is a BUILD_VECTOR with