similar to: [LLVMdev] LLVM and backend

Hi all LLVMdev! Here is a question: I try to understand how I can realize a debugging in LLVM!? I have written a back end for my target and now I need a debug. I asked developers Chris Lattner and Robert L. Bocchino. They recommend me ask the LLVMdev. Is there a tool like "llvm-db" about Robert said? Here a mail from Robert: On Jun 29, 2009, at 17:14 PM, Robert L. Bocchino

Hallo, LLVMdev! I have found you in LLVM Developers page (http://llvm.org/developers.cgi). First thank you for all of your work with LLVM. About: I work with the LLVM Compiler Infrastructure to implement a backend for specific processor xPEC of chip NetX (http://hilscher.com/netx.html). So C-code already possible compile to the native xPEC assembly code (works perfect! LLWM a big

Hello! I am working with LLVM project to compile for specific processor (xPEC-processor from NetX chip, http://hilscher.com/ ). I have done support of this target successfully! Assembler code can be emitted with debug information. LLVM - great!) But now I am looking for generation of machine code for my target. I have seen, that "llc" has option "-filetype". It has

Hi Rudskyy, The place to ask LLVM-related questions is llvmdev at cs.uiuc.edu -- I've cc'd the list. 2009/1/30 Rudskyy <tema13tema at yahoo.de> > I need some help in subject: "Writing an LLVM Compiler Backend"! > > There is a processor with a simple assembly code (http://hilscher.com/ xPEC- processor). I understand, that I need to convert a llvm-IR code to

Do you want to debug the native executables generated by your back-end? What debug info format your native executables support? In general, this is how it works for that case. 1. clang-cc -g generates required debug info in the .bc file. 2. The backend (llc) converts that to Dwarf (or something else as desired by that back-end). 3. Native debuggers like (gdb) understands Dwarf and provide source

Hi Artem, GDB only works with native applications. If you compile your code to a native executable with -g, then debug info should work for you. However, if you've built your own backend, then you may need to add the debug info hooks etc. If you have further questions, please email the llvmdev mailing list instead of me directly, thanks! -Chris On Jun 26, 2009, at 11:11 AM,

----- Original Message ---- > From aaronngray.lists at googlemail.com Mon Jul 27 15:14:40 2009 > From: aaronngray.lists at googlemail.com (Aaron Gray) > Date: Mon, 27 Jul 2009 21:14:40 +0100 > Subject: [LLVMdev] llc - generation of native machine code > > > On Mon, Jul 27, 2009 at 8:25 AM, Rudskyy<tema13tema at yahoo.de> wrote: > > > But now I am looking for

On Mon, Jul 27, 2009 at 8:25 AM, Rudskyy<tema13tema at yahoo.de> wrote: > But now I am looking for generation of machine code for my target. I have > seen, that “llc” has option "-filetype". > > It has default value "-filetype=asm", but has more values, as > "-filetype=obj" and "-filetype=dynlib". > > “obj” is very interesting, but

Hi LLVM developers, As one of the maintainers of AVR target, I want to update WritingAnLLVMBackend document to be familiar with the development of backend, because: 1. The structure of LLVMTargetMachine https://github.com/llvm-mirror/llvm/blob/master/docs/WritingAnLLVMBackend.rst#target-machine has been changed a lot! 2. LLVMInitializeSparcTargetInfo

Hello, LLVMers! How can I force a front end to generate VAARG for accessing varargs parameters? I compile a simple C-code: #include <stdarg.h> int FnVarArgs(int a, ...) { int i,tmp=0; va_list ptArgument; va_start(ptArgument,a); for(i=0;i<9;i++) tmp+= va_arg(ptArgument,int); return tmp; } And then have this bytecode: ; ModuleID = 'main.bc' target

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello devs, I'd like to ask for some advise about adding a backend. I followed the steps at http://llvm.org/docs/WritingAnLLVMBackend.html (also adding the backend to the configure script, so it compiles (on Linux) with LLVM 3.1. However, llvm-build fails with: llvm[0]: Constructing LLVMBuild project information. Usage: llvm-build [options]

On 7/13/2020 21:30, Thomas Lively via llvm-dev wrote: > Part of the problem is that ISel patterns are like their own DSL inside > the TableGen DSL, so keywords like "ins", "outs", and "ops" aren't > keywords at the TableGen level, but rather at the level of the ISel > system implemented with TableGen. Copying existing patterns and reading > the

Thank You. On Fri, Jul 7, 2017 at 10:03 AM, Craig Topper <craig.topper at gmail.com> wrote: > Yes, that error is from instruction selection. I think your legalization > changes worked fine. > > ~Craig > > On Thu, Jul 6, 2017 at 8:21 PM, hameeza ahmed via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> also i further run the following command;

Hi, We have some DSP architectures (kalimba) which have 24-bits as their "minimum addressable unit". So this means that the sizeof a char (and an int and a short for that matter) is 24-bits. I quickly read the posted link WritingAnLLVMBackend.html but did not see an obvious answer to the following question: Is it possible to write a backend that faithfully represents these

On Thu, Mar 25, 2010 at 12:09:36AM -0600, Cam Macdonell wrote: > This patch adds a driver for my shared memory PCI device using the uio_pci > interface. The driver has three memory regions. The first memory region is for > device registers for sending interrupts. The second BAR is for receiving MSI-X > interrupts and the third memory region maps the shared memory. The device only

On Thu, Mar 25, 2010 at 12:09:36AM -0600, Cam Macdonell wrote: > This patch adds a driver for my shared memory PCI device using the uio_pci > interface. The driver has three memory regions. The first memory region is for > device registers for sending interrupts. The second BAR is for receiving MSI-X > interrupts and the third memory region maps the shared memory. The device only

How does LLVM generate machine code for different architectures? For example, the machine code for x86 and amd will vary. How does LLVM convert its IR to machine code for different architectures.Can you please explain the approach? Is it just write two different programs for two different architectures and pass a flag to the compiler based on which machine code you want to generate? Thanks a lot

I want to write a simple backend-specific instrinsic that will just call an instruction. How should I do that? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180924/7faeeb3d/attachment.html>

I want to use LLVM as the main component in my compilation process. In doing so, I know I need to convert a high-level language to another language (python or a custom syntax.) The architecture I'm targeting is non-traditional hardware: microfluidic devices. Microfluidic devices are a specific class of reconfigurable computing; which don't necessarily adhere to a traditional

Hi Johnny, Thanks for this - particularly the tip about cfe-dev. I'm currently trying to coerce lldb to debug these type of architectures (our current toolchain already outputs good dwarf info). However, I'm struggling since lldb has just assumes that the size of a byte is universally 8-bits. At some stage, I *think* at some stage we'd like to derive a compiler, from the "same