similar to: [LLVMdev] PPC calling convention -- how to provide an environment pointer?

On Tue, 2009-01-27 at 08:59 -0800, Stuart Hastings wrote: > I assume you're talking about the 32-bit PowerPC. Also 64-bit, but the two register usage conventions are very close. Someone previously pointed out that R0 is usable as a scratch register, and the CTR can be used. CTR *must* be used for the branch destination out of the ASM trampoline. R0 ends up getting used a lot for constant

> Message: 8 > Date: Tue, 27 Jan 2009 18:00:26 -0500 > From: "Jonathan S. Shapiro" <shap at eros-os.com> > Subject: Re: [LLVMdev] PPC calling convention -- how to provide an > environment pointer? > To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > Message-ID: <1233097226.27873.11.camel at vmx> > Content-Type: text/plain > > On

Shashidhar, Here's it for 32 and 64 bits. https://developer.apple.com/library/mac/#documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html#//apple_ref/doc/uid/TP40002492-SW4 https://developer.apple.com/library/mac/#documentation/DeveloperTools/Conceptual/LowLevelABI/140-x86-64_Function_Calling_Conventions/x86_64.html -Dmitry. On Tue, Feb 26,

This is not, strictly speaking, an LLVM issue, but it is an implementation matter that a compiler using LLVM needs to handle. I've got resolutions for other platforms, but I'm not seeing how to get this done for PowerPC, and I'ld appreciate suggestions or pointers. For BitC procedures that require an environment pointer, our general approach has been to construct a heap-allocated

On Sat, 2012-05-12 at 00:47 -0500, Hal Finkel wrote: > On Tue, 01 May 2012 21:25:29 -0500 > Peter Bergner <bergner at vnet.ibm.com> wrote: > > By the strict letter of the 32-bit ABI, the save and restore of > > r31 at a negative offset of r1 is verboten. The ABI states the > > the stack space below the stack pointer is declared as volatile. > > I actually

On Jun 16, 2009, at 1:17 PMPDT, Anton Korobeynikov wrote: > Hello, Aaron > >> Can I ask what platform ABI's are documented other than Itanium ? > I'd bet all platform ABI are more or less documented. > >> I need to get to understand PIC on x86, x86_64 and PowerPC for the >> COFF and MachO backends. > ABI is normally induced by platform, not by

Hi Chris, Chris Lattner wrote: >> 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved registers. >> However, Linux and Darwin do not have the same set >> of non-callee saved registers. I don't know how to make the if(isDarwin) test >> in here >> > > Take a look at ARM/ARMRegisterInfo.td for an example of this I tried to define Defs just

Hi All, I am looking for a ABI Documentation of the X86 architecture to understand how LLVM converts its IR to X86 target instructions. Please guide me from where i can get the resources. Thanks, Shashidhar -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130226/05855007/attachment.html>

On Fri, 7 Feb 2014, Timothy B. Terriberry wrote: > Martin Storsjo wrote: >> This is required in order to build using the built-in assembler >> in clang. > > These patches break the gcc build (with "Error: bad instruction"). Ah, right, sorry about that. > Documentation I've seen is contradictory on which order ({cond}{size} or > {size}{cond}) is correct.

On Fri, 2 Feb 2007, Nicolas Geoffray wrote: > I have almost completed the implementation of a linux/ppc backend in llvm. Cool! > There were a few things to modify in > lib/Target/PowerPC with a lot of "if (!isDarwin)". Some meta comments: 1. Please don't change PPC -> llvmPPC. I assume that you did this because PPC is a #define in some system header. Please

--- Brady Patterson <brady@spaceship.com> wrote: > On Thu, 27 Jan 2005, John Steele Scott wrote: > > That looks fine to me as well. However, the best solution is > something which > > Luca suggested a few months ago, which is to use the functions > defined in > > altivec.h. These are C functions which map directly to Altivec > machine > > instructions. I

This set of patches converts the way frames gets created from using PUSHes/POPs to using MOVes, thus allowing (in certain cases) to avoid saving/restoring part of the register set. While the place where the (small) win from this comes from varies between CPUs, the net effect is a 1 to 2% reduction on a combined interruption entry and exit when the full state save can be avoided. 1: use MOV

Hello, I noticed that the following code could be improved a little bit further. If the optimization is too tricky for the compiler or something and it's done this way by design forgive me, but in any case i just wanted to point it out. Consider the following C code: extern int mcos(int a); extern int msin(int a); extern int mdiv(int a, int b); int foo(int a, int b) { int a4 =

Dear R helpers,   I have following input files. (Actually they are more than 10 rates but here i am considering only 2 rates to write my problem)   rate1.csv min1        max1            min2          max2          min3           max3 1.05        1.30               1.30          1.65             1.65          1.99   rate2.csv min1        max1            min2          max2          min3          

This is necessary to handle nested traps to the hypervisor more than one deep. I''ve not seen an actually failure relating to this but I''m not quite sure how we''ve managed to get away with not doing it (I suppose multiply nested traps are uncommon). Signed-off-by: Ian Campbell <ian.campbell@citrix.com> --- xen/arch/arm/entry.S | 4 ++++ 1 files changed, 4

Hi everyone, I have almost completed the implementation of a linux/ppc backend in llvm. There were a few things to modify in lib/Target/PowerPC with a lot of "if (!isDarwin)". There are some places where I need help before saying the port is complete. I attached the diff file as a reference 1) In order to generate a creqv instruction before a vararg call, I created a new

Sadly the latest optimization broke completely everything. The asm code isn't gas compliant. the libFLAC linker script has a typo, disabling the asm optimization and/or altivec won't let a correct build anyway. Instant fixes for the asm stuff: sed -i -e"s:;:\#:" on the lpc_asm.s to load address instead of addis+ori you could use lis and la and PLEASE use the @l(register)

I submitted the problem report to clang's bugzilla but no one seems to care so I have to send it to the mailing list. clang 3.7 svn (trunk 229055 as the time I was to report this problem) generates slower code than 3.5 (Apple LLVM version 6.0 (clang-600.0.56) (based on LLVM 3.5svn)) for the following code. It is a "8 queens puzzle" solver written as an educational example. As

The regressions in the performance of generated code, introduced by the llvm 3.6 release, don't seem to be limited to this 8 queens puzzle" solver test case. See... http://www.phoronix.com/scan.php?page=article&item=llvm-clang-3.5-3.6-rc1&num=1 where a bit hit in the performance of the Sparse Matrix Multiply test of the SciMark v2.0 benchmark was observed as well as others.

Using the SciMark 2.0 code from http://math.nist.gov/scimark2/scimark2_1c.zip compiled with the same... make CFLAGS="-O3 -march=native" I am able to reproduce the 22% performance regression in the run time of the Sparse matmult benchmark. For 10 runs of the scimark2 benechmark, I get 998.439+/-0.4828 with the release llvm clang 3.5.1 compiler and 1217.363+/-1.1004 for the current