similar to: [LLVMdev] Qs on building LLVM passes

Hi, The source attached at the bottom is a testcase which causes a back-end error in LLVM 2.4. These types of assembly routines are mainly used in OS kernels. I checked that GCC 4.3 works for this routine. The error messsage is ... Couldn't allocate output reg for constraint 'A'! I just need help or comments so that I could analyze and fix this bug. My

Does anyone succeed at compiling Linux kernel for Sparc v8 architecture? I am currently trying to expand the regime of LLVM to Sparc kernel codes. The following is the initial error messages. Any comment is welcomed. #1. Inline Assembly Code: register struct thread_info *current_thread_info_reg asm("g6"); Error Message: include/asm/thread_info.h:77: error:

Thank your for reply. The reason why these information are needed is that I am trying to extract the program signature (e.g., control flow) out side of the binary. Conventional compiler technique adds extra checking code into the target source or target IR in an invasive manner. Since code generator combines the added code with the original one, they don't need to correlate these two

Keun Soo Yim wrote: > > Hi, > > How to correlate the LLVM IR-leve instructions and memory values > with the machine instructions and memory locations? Can you tell us what goal you are trying to accomplish that requires you to do this? There might be better ways of doing what you want. The answer to your question probably depends on whether you're trying to write a

Hi, How to correlate the LLVM IR-leve instructions and memory values with the machine instructions and memory locations? For example, if CMP instruction in machine ISA is selected for the ICMP instruction in LLVA, with the Instruction datastructure for ICMP, is it possible to get the memory address of CMP instruction? Assume that the code segment base address is given. Similarly, by

Keun Soo Yim wrote: > > Please run… > > $ llvm-gcc -O3 -emit-llvm hello.c -c -o hello.bc > > $ llvm-dis < hello.bc > hello.ll > > The first command is to generate a byte code > > and second is to translate the bytecode to a readable form. > llvm-gcc can emit the textual form directly too: llvm-gcc -O2 -emit-llvm hello.c -S -o hello.ll llvm-gcc -O2 -emit-llvm

On Sep 28, 2008, at 9:46 PM, Keun Soo Yim wrote: > > Does anyone succeed at compiling Linux kernel for Sparc v8 > architecture? > I am currently trying to expand the regime of LLVM to Sparc kernel > codes. > The following is the initial error messages. Any comment is welcomed. > > #1. Inline Assembly The Sparc backend has no active maintainer [1]. This

Hi, This is a simple question about building ARM cross-compiler. What is the building procedure using LLVM 2.4 and GCC front-end 4.2? I used these commands for LLVM, and it is okay. $ ../configure --prefix=/usr/local -target=arm $ make ENABLE_OPTIMIZED=0 $ make ENABLE_OPTIMIZED=0 install Then these commands were used for GCC front-end but this got couple of errors. $ ../configure

Please run. $ llvm-gcc -O3 -emit-llvm hello.c -c -o hello.bc $ llvm-dis < hello.bc > hello.ll The first command is to generate a byte code and second is to translate the bytecode to a readable form. Thanks! From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Alex.Wang Sent: Wednesday, December 24, 2008 10:31 PM To: llvmdev at

Hi everyone. I want to get the llvm IR from the C source code by LLVM-GCC. But I am not familiar with those command line arguments. Can anyone give me a guidance? Thank you very much for any help. Good luck. -- Best regards. -------------- next part -------------- An HTML attachment was scrubbed... URL:

On 2008-09-29 07:46, Keun Soo Yim wrote: > Does anyone succeed at compiling Linux kernel for Sparc v8 architecture? > I am currently trying to expand the regime of LLVM to Sparc kernel codes. > The following is the initial error messages. Any comment is welcomed. > > #1. Inline Assembly > > > > Code: > > register struct thread_info

Mark Kromis wrote: > On Dec 27, 2008, at 7:41 PM, Misha Brukman wrote: >> 2008/12/27 Mark Kromis <greybird at mac.com> >> Just a curiosity question, why push for gtest vs Boost Test or a >> different test suite? >> I normally use Boost, and their test suite, so I'm more familiar with >> that. So I was wondering is one better then the other, or is it

2008/12/28 Keun Soo Yim <yim6 at illinois.edu> > This is a simple question about building ARM cross-compiler. > What is the building procedure using LLVM 2.4 and GCC front-end 4.2? > > I used these commands for LLVM, and it is okay. > > $ ../configure --prefix=/usr/local -target=arm > $ make ENABLE_OPTIMIZED=0 > $ make ENABLE_OPTIMIZED=0 install > > Then

Currently I have a trick to extract the correlation information of LLVA and ISA. By adding an intrinsic instruction and comparing the emitted binary with the original one. The location of machine instruction that I am interested in is calculated relative to the intrinsic instruction. Unless I change the original instruction with the intrinsic having a same size, this needs many iterations as much

Dear helpers, I'm using R version 2.8.0. Suppose that I have a small data set like below. [,1] [,2] [,3] [,4] a 1 1 0 0 b 0 1 1 0 c 1 1 1 0 d 0 1 1 1 First, I'd like to find row sum of values uniquely present in each row, but only sequentially from the top row, meaning that if the value is shown in the above row(s) already, the

i cant get one the internet using wine how can i fix this problem i tryed using ymlite and yahoo messenger

As &qs->qs_lock is also acquired by the timer o2net_idle_timer() which executes under softirq context, code executing under process context should disable irq before acquiring the lock, otherwise deadlock could happen if the process context hold the lock then preempt by the timer. Possible deadlock scenario: o2quo_make_decision (workqueue) -> spin_lock(&qs->qs_lock);

As &qs->qs_lock is also acquired by the timer o2net_idle_timer() which executes under softirq context, code executing under process context should disable irq before acquiring the lock, otherwise deadlock could happen if the process context hold the lock then preempt by the timer. Possible deadlock scenario: o2quo_make_decision (workqueue) -> spin_lock(&qs->qs_lock);

On Apr 4, 2015, at 7:19 PM, Richard Flint <richard.flint at gmail.com> wrote: > More extensive debugging by running the driver sudo ./nutdrv_qx -u root -a MY_UPS -DDDDDD indicates the driver works normally then will randomly stop working at stop "send: QS". The debug logs show values successfully retrieved repeatedly until something like: > .... > Quick update... >

Hi Jan, I am now reading quota support in ocfs2 and have some qs. Wish you can help me clarify it. Thanks. ocfs2_quota_write: In the comment, you said that "we know the transaction is already started", so it should be called within a transaction. But in this function, we call ocfs2_extend_no_holes and ocfs2_simple_size_update which will start another transaction. So we can survive