similar to: [LLVMdev] [llvm-commits] [llvm] r58505 - /llvm/trunk/lib/VMCore/Type.cpp

On Mon, 2008-08-18 at 08:50 -0700, Eli Friedman wrote: > On Mon, Aug 18, 2008 at 6:31 AM, <Sachin.Punyani at microchip.com> wrote: > > assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && > > "Invalid operand expansion"); > > > > LOAD node has two values but the assertion checks N->getNumValues() == 1 >

>I am assuming a 16-bit value will be stored in a pair of 8-bit > registers? One related question is how to make sure that the correct register pair is allocated to the16-bit quantity when using two 8-bit operations. In other words, how we can make sure that the 16-bit pointer is stored into [AH, AL] and not in [AH, BL] ? i.e. GR8 = [ AH, BH, AL, BL]; GR16 = [AX, BX] ; // AX, BX

On Tue, Aug 19, 2008 at 8:07 AM, sanjiv gupta <sanjiv.gupta at microchip.com> wrote: > On Mon, 2008-08-18 at 08:50 -0700, Eli Friedman wrote: >> On Mon, Aug 18, 2008 at 6:31 AM, <Sachin.Punyani at microchip.com> wrote: >> > assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && >> > "Invalid operand

On Jul 3, 2009, at 4:01 AM, Sanjiv Gupta wrote: > Sachin.Punyani at microchip.com wrote: >> >> Hi, >> >> >> >> In PHI node elimination pass to insert the copy in the predecessor >> block, there is a check if terminator is not an invoke instruction >> then place the copy there only. However for invoke terminator >> instruction a safe

Sachin.Punyani at microchip.com wrote: > > Hi, > > > > In PHI node elimination pass to insert the copy in the predecessor > block, there is a check if terminator is not an invoke instruction > then place the copy there only. However for invoke terminator > instruction a safe position is located for copy insertion. > > > > My doubt is why is this safe

> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of Bill Wendling > Sent: Friday, September 19, 2008 4:38 AM > > On Thu, Sep 18, 2008 at 7:12 AM, <Sachin.Punyani at microchip.com> wrote: > > What changes would be required in LLVM to support illegal pointer type? > > > Hi Sachin, >

Hi Sachin, llvm-dev, I've just committed a new PBQP solver which, among other things, should take care of this bug. Please let me know how it works out for you. Cheers, Lang. On Tue, Dec 15, 2009 at 5:54 PM, Lang Hames <lhames at gmail.com> wrote: > Hi Sachin, > > Yes. Bernhard Scholz and I have just discussed a fix for this. I hope to > commit it in the next few days. I

I am assuming a 16-bit value will be stored in a pair of 8-bit registers? If so, add pseudo register which represent pairs of 8-bit registers. Add them to a pseudo register class. This allows you to mark i16 "legal". The difficult part is then to figure out how to lower these 16-bit operations into 8-bit ones. You probably need to custom lower a bunch of them with target

On Fri, Aug 7, 2009 at 9:18 AM, <Sanjiv.Gupta at microchip.com> wrote: > These URLs don't work for me. How do I know what is broken? > It builds fine on my x86 linux box. Why don't the URLs work for you? In this case the problem was just because llvm.org went down. When an "svn" step fails; i.e., the line after "BUILD FAILED:", the problem is usually

Hi, I want to emit the debug information in assembly through assembler directives. Also I don't want to emit debug information in sections (like Dwarf). Instead the debug information will be interspersed with the assembly. However in LLVM, debug info (e.g. stoppoint) is read and made part of the DAG only when DwarfWriter is registered. How can I emit the debug information in assembly

I don't know what failed on llvm-ppc-linux. The build works on my i386-linux. I can't access the said URL. It says "connection refused". - Sanjiv -------- Original Message -------- Subject: buildbot failure in llvm on llvm-ppc-linux Date: Tue, 16 Jun 2009 09:20:25 -0700 From: buildbot at google1.osuosl.org To: Sanjiv Gupta <sanjiv.gupta at microchip.com> CC:

On Aug 7, 2009, at 10:13 AM, Daniel Dunbar wrote: > On Fri, Aug 7, 2009 at 9:18 AM, <Sanjiv.Gupta at microchip.com> wrote: >> These URLs don't work for me. How do I know what is broken? >> It builds fine on my x86 linux box. > > Why don't the URLs work for you? > I suspect the corporate firewall is blocking outgoing connections on port 8011. -jim > In

Hi, In PHI node elimination pass to insert the copy in the predecessor block, there is a check if terminator is not an invoke instruction then place the copy there only. However for invoke terminator instruction a safe position is located for copy insertion. My doubt is why is this safe location search done only for invoke instruction and not for other terminators such as branch.

Hi All, I have some doubt in LLVM Type Legalizer. How will LOAD:i8 with an i16 operand be lowered in type legalizer? (i16 type is not legal for our target) Following assertion in function ExpandIntegerOperand (file LegalizeIntegerTypes.cpp) is not allowing us to change LOAD node. assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&

These URLs don't work for me. How do I know what is broken? It builds fine on my x86 linux box. -----Original Message----- From: buildbot at google1.osuosl.org [mailto:buildbot at google1.osuosl.org] Sent: Friday, August 07, 2009 5:12 PM To: Sanjiv Kumar Gupta - I00171 Cc: llvm-testresults at cs.uiuc.edu Subject: buildbot failure in llvm on llvm-i686-linux The Buildbot has detected a new

Hi Lang, Thanks for your inputs on the problem. I was just curious to know if you got any opportunity to work on the solution for this. Regards Sachin > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of Sachin.Punyani at microchip.com > Sent: Tuesday, November 17, 2009 12:00 PM > Subject: Re: [LLVMdev] Crash

Hi, Probably I did not mention my question correctly. I need to emit declarations of the libcalls (that are made in the current module) at the beginning of the assembly file. The class "Module" does not maintain any list of the libcalls made during the program. Although, it maintains lists of all the global variables and functions in the current module. Traversing each

Sachin, On Feb 24, 2009, at 12:27 AM, Sachin.Punyani at microchip.com wrote: > Hi, > > I want to emit the debug information in assembly through assembler > directives. Also I don’t want to emit debug information in sections > (like Dwarf). Instead the debug information will be interspersed > with the assembly. However in LLVM, debug info (e.g. stoppoint) is > read

Hi Sachin, Yes. Bernhard Scholz and I have just discussed a fix for this. I hope to commit it in the next few days. I will let you know as soon as it goes in to the mainline. Regards, Lang. On Tue, Dec 15, 2009 at 5:34 PM, <Sachin.Punyani at microchip.com> wrote: > Hi Lang, > > Thanks for your inputs on the problem. I was just curious to know if you > got any opportunity to

Hi Sachin, Confirmed: This is being caused by a subtle issue in the heuristic PBQP solver. Specifically: R1/R2 reductions as currently implemented can, on rare occasions, lead to the heuristic solver failing to find a finite cost solution, even though one exists. The infinite cost solution will always be in violation of some rule of register allocation (failing to handle an interference, or