similar to: [LLVMdev] llvm-gcc doesnt honor volatile quantifier of the array type?

This looks wrong to me, though the x86 backend produces code that does the right thing (reads each element once). If you change the code (see below) to read each element twice, llvm-gcc still does the right thing but llvm-g++ does not (i.e. it fails to read aech location twice). Current versions of gcc/g++ also look wrong. All 4 compilers (gcc,g++,llvm-gcc,llvm-g++) do the right thing when

On Mon, Dec 6, 2010 at 6:16 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: >> -----Original Message----- >> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] >> On Behalf Of Peter Collingbourne >> Sent: Monday, December 06, 2010 2:56 PM >> To: David Neto >> Cc: cfe-dev at cs.uiuc.edu; llvmdev at cs.uiuc.edu >>

Hi, Thanks, John, I just forgot the multi-thread issue. I'll write my own pass to handle this as for my project, it is just single-thread case. Sheng. Date: Thu, 22 May 2008 09:30:45 -0500 > From: John Criswell <criswell at cs.uiuc.edu> > Subject: Re: [LLVMdev] Eliminate Store-Load pair even the LoadInst is > volatile > To: LLVM Developers Mailing List

> -----Original Message----- > From: David Neto [mailto:dneto.llvm at gmail.com] > Sent: Tuesday, December 07, 2010 1:03 PM > To: Villmow, Micah > Cc: cfe-dev at cs.uiuc.edu; llvmdev at cs.uiuc.edu > Subject: Re: [cfe-dev] [LLVMdev] OpenCL support > > On Mon, Dec 6, 2010 at 6:16 PM, Villmow, Micah <Micah.Villmow at amd.com> > wrote: > >> -----Original

> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Peter Collingbourne > Sent: Monday, December 06, 2010 2:56 PM > To: David Neto > Cc: cfe-dev at cs.uiuc.edu; llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] [cfe-dev] OpenCL support > > Hi David, > > On Mon, Dec 06, 2010 at 11:14:42AM -0500,

Hi all, I put a case into llvm and got the following .ll code: ... %r1419_0_0_0_i376 = alloca i32 ; <i32*> [#uses=2] ... %tmp1476_i = lshr i32 %tmp1226_i, 24 ; <i32> [#uses=1] store i32 %tmp1476_i, i32* %r1419_0_0_0_i376, align 4 %tmp1505_i = volatile load i32* %r1419_0_0_0_i376, align 4 ; <i32> [#uses=1] %tmp1542_i = getelementptr [256 x i8]* @Te, i32 0, i32 %tmp1505_i ...

Here is the example code: class A { const int x[5]; public: //A() { x[0] = 1; x[1] = 1; x[2] = 2; x[3] = 3; x[4] = 4; } A():x((const int[5]){1,2,3,4,5}) {} int getV(int idx) { return x[idx];} }; //const int A::x[5] = { 1, 2, 3, 4, 5 }; int main() { A a; return a.getV(1); } gcc 4.1.2 can compile the above code. llvm-gcc reports: x.cpp: In constructor \u2018A::A()\u2019: x.cpp:5:

Hi David, On Mon, Dec 06, 2010 at 11:14:42AM -0500, David Neto wrote: > >> It > >> seems it would be a good idea to transform the code so that uses of x > >> become loads and stores from memory, and the address for that memory > >> is returned by a builtin function that itself is dependent on work > >> group ids. > >> > >> I'm

I have some code generated with llvm-g++ and llvm-link that includes a tail call that is confusing me for two reasons: 1) I am not sure why it is a tail call (i.e. it does not look like it is in the tail position) 2) When I instrument the code using my opt pass, none of the instrumentation functions in the callee get called, leading me to believe that some funny business is going on. Below I

Hi, I was confronted with some trouble, I describe the trouble in my journal http://trac.xapian.org/wiki/GSoC2014/Posting%20list%20encoding%20improvements/Journal#May10 And corresponding code is in my git. Would you like to give me some help? ------------------ Shangtong Zhang,Second Year Undergraduate, School of Computer Science, Fudan University, China. -------------- next part

Current llvm-gcc 4.2 building failed on X86-64, here is the dump information: xgcc -B/home/zsth/projects/llvm.org/build/cfe4.2obj/./prev-gcc/ -B/home/zsth/projects/llvm.org/install/x86_64-unknown-linux-gnu/bin/ -I../../../cfe4.2/libcpp -I. -I../../../cfe4.2/libcpp/../include -I../../../cfe4.2/libcpp/include -DENABLE_LLVM -g -O2 -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes

Hello, I am wondering if anyone could help me out with the following questions: 1. How to uninstall Samba? 2. How to install/upgrade/uninstall Samba from Mandrake 9.0 to the latest Samba version via source code (I noticed that MDK9 installed Samba to different places. And the document:"Using Samba" mentioned the file "inetd.conf" but I couldn't find it in MDK9.)

Hi I am completely new to LLVM, and I am trying to explore the alias analysis part of it. It seems to me that -basicaa is the most simple alias analysis pass in LLVM. So I would like to try and make it work (to see some alias analysis results of some sample bit code). What I have done is that I ---make lib/Analysis/BasicAliasAnalysis.cpp into a .so file ---write a sample c program, hello.c,

Gordon Henriksen wrote: > On 2008-03-29, at 00:57, Nick Lewycky wrote: > >> Gordon Henriksen wrote: >> >>> What blocks would a phi node in %catch require for a case like this? >>> >>> define i8 @f(i1 %b) { >>> entry: >>> b label %try >>> try: unwinds to %catch >>> b i1 %b, label %then, label %else

Hi all, I have problem with ExtractCodeRegion (CodeExtractor.cpp). My original program is as follows. bb: ... %tmp.15 = load %struct.MYSQL_ROWS** %3, align 4 ... bb1: ... %tmp.1 = load %struct.MYSQL_ROWS** %6, align 4 ... bb4: ; preds = %bb1, %bb, %entry %tmp.0 = phi %struct.MYSQL_ROWS* [ null, %entry ], [ %tmp.15, %bb ], [ %tmp.1, %bb1 ]

Hello, I have two for loops (one inside the other), that after indvars, looprotate, etc. (the important here is the loop rotate), is similar to this (I've stripped the real operations): define i32 @f() nounwind { entry: br label %bb1 bb1: ; preds = %bb3, %bb1, %entry %i.0.reg2mem.0.ph = phi i32 [ 0, %entry ], [ %i.0.reg2mem.0.ph, %bb1 ], [ %indvar.next9, %bb3 ] ;

So my best bet is to try and work in reg2mem mode and then go back to mem2reg? I'm curious, it seems though when you split a block that the phis get updated, right? On Thu, Feb 2, 2012 at 5:05 PM, Eric Christopher <echristo at apple.com> wrote: > Not that I'm aware of. > > -eric > > On Feb 2, 2012, at 3:47 PM, Ryan Taylor wrote: > > So essentially I'm

On May 22, 2014, at 3:51 PM, Chandler Carruth <chandlerc at google.com> wrote: > > On Thu, May 22, 2014 at 4:42 PM, Louis Gerbarg <lgg at apple.com> wrote: > The problem that the above transform is technically illegal because “When indexing into a (optionally packed) structure, only i32 integer constants are allowed (when using a vector of indices they must all be the same

Hi all, Suppose in a CFG bb1 has two succesor bb3 and bb4, and bb3 has two predecessor bb1 and bb2. Now how can I insert a basic block between bb1 and bb3 that at the edge bb1-->bb3 . In general how can I insert a basic block on an edge? Regards, Chayan

---------- Forwarded message ---------- From: Ryan Taylor <ryta1203 at gmail.com> Date: Mon, Feb 6, 2012 at 10:36 AM Subject: Re: [LLVMdev] Updating PHI for Instruction Domination? To: Eric Christopher <echristo at apple.com> Since I'm not sure which instructions I might want to replicate, would it be possible to cast the Value from "PHINode::getIncomingValue" to