similar to: [LLVMdev] Doubt over lib call generation

Displaying 20 results from an estimated 2000 matches similar to: "[LLVMdev] Doubt over lib call generation"

2009 Jan 12
0
[LLVMdev] Doubt over lib call generation
Hi, > Consider the case in Sparc or ARM can you please provide a testcase in bitcode (or LLVM assembler) form. Thanks, Duncan.
2009 Jan 12
1
[LLVMdev] Doubt over lib call generation
> > Hi, > > > Consider the case in Sparc or ARM > > can you please provide a testcase in bitcode (or > LLVM assembler) form. > Please find the bitcode file and C file attached with. Regards Sachin > Thanks, > > Duncan. -------------- next part -------------- A non-text attachment was scrubbed... Name: trysparc.bc Type: application/octet-stream Size: 476
2010 Jan 31
0
Package ismev, gpd.fit, and interpretation for statistics of extreme values
Dear All, I have a question about package "ismev", its function "gpd.fit", and interpretation of the results. I used the package ismev to do an extreme value analysis on a fire dataset. Two variables are used in the analysis. The focal variable is acreage burned per fire, ranging from 1 to 5000 acres per fire. In total, there are 69,980 observations. The date covers
2008 Dec 18
2
[LLVMdev] Doubts about lowering of UMUL_LOHI
Hi, When expanding multiply operation in LegalizeTypes LLVM generates some nodes such as UMUL_LOHI (please refer file LegalizeIntegerTypes.cpp - function - ExpandIntegerResult). However while lowering this operation in LegalizeDAG (please refer file LegalizeDAG.cpp - function - LegalizeOp) the comment says "These nodes will only be produced by target-specific lowering.....".
2013 Dec 16
0
vectorizaciones
Hola, De esta manera sí funciona: #----------------------------------------------- #................... vec1a <- as.vector(1:3) n1a <- 3 n2a <- 3 #P1a <- matrix(rnorm(30),nrow=3) #P2a <- matrix(rnorm(30),nrow=3) Ka <- 10 n.val <- 30 # En forma de funcion producto <- function(n1a,n2a,Ka,vec1a,n.val){ # A eliminar una vez compruebes que la vectorización funciona
2009 Jul 03
2
[LLVMdev] Doubt in PHI node elimination
Hi, In PHI node elimination pass to insert the copy in the predecessor block, there is a check if terminator is not an invoke instruction then place the copy there only. However for invoke terminator instruction a safe position is located for copy insertion. My doubt is why is this safe location search done only for invoke instruction and not for other terminators such as branch.
2009 Jul 03
0
[LLVMdev] Doubt in PHI node elimination
Sachin.Punyani at microchip.com wrote: > > Hi, > > > > In PHI node elimination pass to insert the copy in the predecessor > block, there is a check if terminator is not an invoke instruction > then place the copy there only. However for invoke terminator > instruction a safe position is located for copy insertion. > > > > My doubt is why is this safe
2009 Jul 07
1
[LLVMdev] Doubt in PHI node elimination
On Jul 3, 2009, at 4:01 AM, Sanjiv Gupta wrote: > Sachin.Punyani at microchip.com wrote: >> >> Hi, >> >> >> >> In PHI node elimination pass to insert the copy in the predecessor >> block, there is a check if terminator is not an invoke instruction >> then place the copy there only. However for invoke terminator >> instruction a safe
2013 Dec 16
2
vectorizaciones
Hola a tod en s, tengo que hacer una operación con matrices que lleva un doble bucle. He intentado vectorizarlo pero sin mucho éxito con la función "Vectorize". ¿sabríais de alguna manera de evitar los bucles o de que funcionase Vectorize? Adjunto un ejemplo #................... vec1a <- as.vector(1:3) n1a <- 3 n2a <- 3 P1a <- matrix(rnorm(30),nrow=3) P2a <-
2009 Dec 10
2
[LLVMdev] Doubt related to scheduling with shift operation
Hi, For the case, please see the ".ll" file attached. Here I am doing a right shift on 32 bits by constant amount (specifically by 8). My target is an 8-bit target. Therefore while performing a shift (right or left) on long (32 bits) it is legalized in 4 smaller units. After performing the shift, this value should be stored at the same location. So order of the stores does
2009 Jun 22
1
[LLVMdev] Floating point comparison doubt
Hi, In unordered floating point comparison before making a call for comparison proper one node called UO_F32 is generated. In targets this node is replaced with a call to __unordsf2. My doubts here 1) What are these UO_F32 and O_F32 nodes for? 2) What is this function (__unordsf2) supposed to do? Regards Sachin -------------- next part -------------- An HTML attachment was
2009 Dec 11
0
[LLVMdev] Doubt related to scheduling with shift operation
Hi, > My target is an 8-bit target. Therefore while performing a shift (right > or left) on long (32 bits) it is legalized in 4 smaller units. After > performing the shift, this value should be stored at the same location. > So order of the stores does matter. But all 4 stores are parallel in the > code and do not have any control flow dependency between them. Therefore >
2009 Nov 15
2
resampling problem counting number of means above a specific value
I am trying to modify some code from Good 2005. I am trying to resample the mean of 8 values and then count how many times the resampled mean is greater than 10. But my count of means above 10 is coming out as zero, which I know isn't correct. I would appreciate it if someone could look at the code below and tell me what I am doing wrong. Many thanks, Graham > LL<-
2008 Apr 02
0
Using file to handle a direcoty, recurse question.
Alright, going ot ask this question in advance of doing bone headed tests. I have one application that does not understand the idea of /usr/local/ and insists on populating /usr. Of course it is closed source and commercial and it is the one they want to use. Below is the list of junk it shoves in /usr/share. Between the Type Reference guide and another email , I believe I can move this tree
2008 Dec 18
0
[LLVMdev] Doubts about lowering of UMUL_LOHI
On Wed, Dec 17, 2008 at 11:49 PM, <Sachin.Punyani at microchip.com> wrote: > 2) Why is custom legalization of this node not allowed? No target has needed it so far. Why do you need it? > 3) My target does not have any instruction directly matching to this > operation. How should this node be legalized? If your target doesn't have this operation, you should mark
2008 Oct 26
0
[LLVMdev] Turning on LegalizeTypes by default
On Oct 26, 2008, at 1:03 AM, Duncan Sands wrote: > Hi all, I plan to turn on the new type legalization infrastructure > "LegalizeTypes" by default tomorrow. This is a redesign/ > reimplementation > of the logic currently in LegalizeDAG that turns (for example) 64 bit > arithmetic on a 32 bit machine into a series of 32 bit operations. > As well > as being a
2008 Oct 26
6
[LLVMdev] Turning on LegalizeTypes by default
Hi all, I plan to turn on the new type legalization infrastructure "LegalizeTypes" by default tomorrow. This is a redesign/reimplementation of the logic currently in LegalizeDAG that turns (for example) 64 bit arithmetic on a 32 bit machine into a series of 32 bit operations. As well as being a cleaner design, it also supports code generation for arbitrary precision integers such as
2009 Dec 15
2
[LLVMdev] Crash in PBQP register allocator
Hi Lang, Thanks for your inputs on the problem. I was just curious to know if you got any opportunity to work on the solution for this. Regards Sachin > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of Sachin.Punyani at microchip.com > Sent: Tuesday, November 17, 2009 12:00 PM > Subject: Re: [LLVMdev] Crash
2009 Dec 15
0
[LLVMdev] Crash in PBQP register allocator
Hi Sachin, Yes. Bernhard Scholz and I have just discussed a fix for this. I hope to commit it in the next few days. I will let you know as soon as it goes in to the mainline. Regards, Lang. On Tue, Dec 15, 2009 at 5:34 PM, <Sachin.Punyani at microchip.com> wrote: > Hi Lang, > > Thanks for your inputs on the problem. I was just curious to know if you > got any opportunity to
2012 Feb 07
0
[LLVMdev] DAG optimization and lowering algorithm
On Mon, Feb 6, 2012 at 11:54 PM, Demikhovsky, Elena <elena.demikhovsky at intel.com> wrote: > Hi, > > I'm trying to build code for very short function and I encounter with a problem (or bug) in DAG selection algotithm. > I have a node that was created in Combine(BeforeLegalizeTypes) and should be optimized in Combine(AfterLegalizeTypes). But LegalizeTypes() did not change