similar to: [LLVMdev] how to get the llvm IR from C source code?

Please run. $ llvm-gcc -O3 -emit-llvm hello.c -c -o hello.bc $ llvm-dis < hello.bc > hello.ll The first command is to generate a byte code and second is to translate the bytecode to a readable form. Thanks! From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Alex.Wang Sent: Wednesday, December 24, 2008 10:31 PM To: llvmdev at

Keun Soo Yim wrote: > > Please run… > > $ llvm-gcc -O3 -emit-llvm hello.c -c -o hello.bc > > $ llvm-dis < hello.bc > hello.ll > > The first command is to generate a byte code > > and second is to translate the bytecode to a readable form. > llvm-gcc can emit the textual form directly too: llvm-gcc -O2 -emit-llvm hello.c -S -o hello.ll llvm-gcc -O2 -emit-llvm

Hi, I have couple of questions that those who design unconventional passes would be interested in. 1. How to move a virtual register data to another new virtual register? It seems like that there is no LLVM instruction similar to mov machine instruction. Arithmetic or logical operators could be used for integer variables but what about pointer variables? 2. What is

Hi, The source attached at the bottom is a testcase which causes a back-end error in LLVM 2.4. These types of assembly routines are mainly used in OS kernels. I checked that GCC 4.3 works for this routine. The error messsage is ... Couldn't allocate output reg for constraint 'A'! I just need help or comments so that I could analyze and fix this bug. My

Thank your for reply. The reason why these information are needed is that I am trying to extract the program signature (e.g., control flow) out side of the binary. Conventional compiler technique adds extra checking code into the target source or target IR in an invasive manner. Since code generator combines the added code with the original one, they don't need to correlate these two

Does anyone succeed at compiling Linux kernel for Sparc v8 architecture? I am currently trying to expand the regime of LLVM to Sparc kernel codes. The following is the initial error messages. Any comment is welcomed. #1. Inline Assembly Code: register struct thread_info *current_thread_info_reg asm("g6"); Error Message: include/asm/thread_info.h:77: error:

Keun Soo Yim wrote: > > Hi, > > How to correlate the LLVM IR-leve instructions and memory values > with the machine instructions and memory locations? Can you tell us what goal you are trying to accomplish that requires you to do this? There might be better ways of doing what you want. The answer to your question probably depends on whether you're trying to write a

Hi, How to correlate the LLVM IR-leve instructions and memory values with the machine instructions and memory locations? For example, if CMP instruction in machine ISA is selected for the ICMP instruction in LLVA, with the Instruction datastructure for ICMP, is it possible to get the memory address of CMP instruction? Assume that the code segment base address is given. Similarly, by

On Sep 28, 2008, at 9:46 PM, Keun Soo Yim wrote: > > Does anyone succeed at compiling Linux kernel for Sparc v8 > architecture? > I am currently trying to expand the regime of LLVM to Sparc kernel > codes. > The following is the initial error messages. Any comment is welcomed. > > #1. Inline Assembly The Sparc backend has no active maintainer [1]. This

Hi, This is a simple question about building ARM cross-compiler. What is the building procedure using LLVM 2.4 and GCC front-end 4.2? I used these commands for LLVM, and it is okay. $ ../configure --prefix=/usr/local -target=arm $ make ENABLE_OPTIMIZED=0 $ make ENABLE_OPTIMIZED=0 install Then these commands were used for GCC front-end but this got couple of errors. $ ../configure

On 2008-09-29 07:46, Keun Soo Yim wrote: > Does anyone succeed at compiling Linux kernel for Sparc v8 architecture? > I am currently trying to expand the regime of LLVM to Sparc kernel codes. > The following is the initial error messages. Any comment is welcomed. > > #1. Inline Assembly > > > > Code: > > register struct thread_info

Mark Kromis wrote: > On Dec 27, 2008, at 7:41 PM, Misha Brukman wrote: >> 2008/12/27 Mark Kromis <greybird at mac.com> >> Just a curiosity question, why push for gtest vs Boost Test or a >> different test suite? >> I normally use Boost, and their test suite, so I'm more familiar with >> that. So I was wondering is one better then the other, or is it

Hi all, I am trying to disassemble *.bc to assemble code by using llvm-dis command, but what I got is like the following. So how could I get the assemble code like objdump? I mean the memory address for each instruction. Thanks Qiuyu llvm-dis: .text .align 16 .globl adpcm_coder .type adpcm_coder, @function adpcm_coder: .LBBadpcm_coder_0: # entry sub %ESP, 116 mov DWORD PTR [%ESP + 12],

On Tue, 30 Nov 2004, Tanu Sharma wrote: > I have trouble using the llvm tools.Some of the errors are : > > $ llvm-dis prog.bc > $ llvm-dis: Invalid Top Level Block Length! Type:1, Size:456 (Vers=0, Pos=12) Can you explain how you generated this bytecode file? It looks corrupted or something. Also, can you send the actual bytecode file itself? Thanks! -Chris >

Hi, I am trying to generate LLVM bytecode using CLANG and I ran into the following problem. If I run clang with the -emit-llvm option and then try to get a textual representation of the output using llvm-dis, the latter crashes because of a failed assertion in BitCodeReader.cpp, mentioning a "Type mismatch in value table" (the exact error message is appended at the end of this email).

On Tue, Jul 15, 2014 at 10:46 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 7/15/14, 9:32 AM, Gaoyao Xiao wrote: > > Hi, > > > I have some IR files which can be compiled using llc-3.0 and gcc-4.6.3. > I want to instrument these IR files. My instrumentation pass is implemented > under LLVM-3.5 and some data structures in LLVM-3.5 are not available on >

Hi, When I execute the command bellow: $llvm-dis Example.bc -o Example.ll I get the following wrong message: llvm-dis:Bitcode stream should be a multiple of 4 bytes in length Who can help me? 2010-04-07 yiqiuping1986 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100407/2cd7a437/attachment.html>

Hi, I just updated my LLVM sources from CVS/HEAD and rebuilt them. And I downloaded the GCC4 frontend from the 1.9 release. Now I cannot compile anything, since GCC frontend seems to produce BC files that cannot be read by llvm-dis, llc and other utils. llvm-dis shows a following message: Bytecode formats < 7 are not longer supported. Use llvm-upgrade. (Vers=6, Pos=9) But since the new

Hi, I have some IR files which can be compiled using llc-3.0 and gcc-4.6.3. I want to instrument these IR files. My instrumentation pass is implemented under LLVM-3.5 and some data structures in LLVM-3.5 are not available on LLVM-3.0, such as *AttributeSet* in *Attribute.h*. I tried to compile my instrumentation pass under LLVM-3.0 and it failed due to missing data types. So I am asking whether

On Monday 29 November 2004 19:39, Chris Lattner wrote: > > > Alternatively, if you don't want to do that, you can build mem2reg into > > > your pass if it works better. To do this, your pass needs to > > > 'addRequired' DominatorTree and DominatorFrontier, then use the > > > interfaces exposed through > > >