similar to: [LLVMdev] How to correlate LLVA with native ISA

Keun Soo Yim wrote: > > Hi, > > How to correlate the LLVM IR-leve instructions and memory values > with the machine instructions and memory locations? Can you tell us what goal you are trying to accomplish that requires you to do this? There might be better ways of doing what you want. The answer to your question probably depends on whether you're trying to write a

Thank your for reply. The reason why these information are needed is that I am trying to extract the program signature (e.g., control flow) out side of the binary. Conventional compiler technique adds extra checking code into the target source or target IR in an invasive manner. Since code generator combines the added code with the original one, they don't need to correlate these two

Currently I have a trick to extract the correlation information of LLVA and ISA. By adding an intrinsic instruction and comparing the emitted binary with the original one. The location of machine instruction that I am interested in is calculated relative to the intrinsic instruction. Unless I change the original instruction with the intrinsic having a same size, this needs many iterations as much

Hi, I have couple of questions that those who design unconventional passes would be interested in. 1. How to move a virtual register data to another new virtual register? It seems like that there is no LLVM instruction similar to mov machine instruction. Arithmetic or logical operators could be used for integer variables but what about pointer variables? 2. What is

Hi, The source attached at the bottom is a testcase which causes a back-end error in LLVM 2.4. These types of assembly routines are mainly used in OS kernels. I checked that GCC 4.3 works for this routine. The error messsage is ... Couldn't allocate output reg for constraint 'A'! I just need help or comments so that I could analyze and fix this bug. My

Does anyone succeed at compiling Linux kernel for Sparc v8 architecture? I am currently trying to expand the regime of LLVM to Sparc kernel codes. The following is the initial error messages. Any comment is welcomed. #1. Inline Assembly Code: register struct thread_info *current_thread_info_reg asm("g6"); Error Message: include/asm/thread_info.h:77: error:

On Sep 28, 2008, at 9:46 PM, Keun Soo Yim wrote: > > Does anyone succeed at compiling Linux kernel for Sparc v8 > architecture? > I am currently trying to expand the regime of LLVM to Sparc kernel > codes. > The following is the initial error messages. Any comment is welcomed. > > #1. Inline Assembly The Sparc backend has no active maintainer [1]. This

Keun Soo Yim wrote: > > Please run… > > $ llvm-gcc -O3 -emit-llvm hello.c -c -o hello.bc > > $ llvm-dis < hello.bc > hello.ll > > The first command is to generate a byte code > > and second is to translate the bytecode to a readable form. > llvm-gcc can emit the textual form directly too: llvm-gcc -O2 -emit-llvm hello.c -S -o hello.ll llvm-gcc -O2 -emit-llvm

Please run. $ llvm-gcc -O3 -emit-llvm hello.c -c -o hello.bc $ llvm-dis < hello.bc > hello.ll The first command is to generate a byte code and second is to translate the bytecode to a readable form. Thanks! From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Alex.Wang Sent: Wednesday, December 24, 2008 10:31 PM To: llvmdev at

Hi everyone. I want to get the llvm IR from the C source code by LLVM-GCC. But I am not familiar with those command line arguments. Can anyone give me a guidance? Thank you very much for any help. Good luck. -- Best regards. -------------- next part -------------- An HTML attachment was scrubbed... URL:

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. The Physical Function and Virtual Function drivers using the SR-IOV APIs will come soon! Major changes from

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. The Physical Function and Virtual Function drivers using the SR-IOV APIs will come soon! Major changes from

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. The Physical Function and Virtual Function drivers using the SR-IOV APIs will come soon! Major changes from

Hi, This is a simple question about building ARM cross-compiler. What is the building procedure using LLVM 2.4 and GCC front-end 4.2? I used these commands for LLVM, and it is okay. $ ../configure --prefix=/usr/local -target=arm $ make ENABLE_OPTIMIZED=0 $ make ENABLE_OPTIMIZED=0 install Then these commands were used for GCC front-end but this got couple of errors. $ ../configure

On 2008-09-29 07:46, Keun Soo Yim wrote: > Does anyone succeed at compiling Linux kernel for Sparc v8 architecture? > I am currently trying to expand the regime of LLVM to Sparc kernel codes. > The following is the initial error messages. Any comment is welcomed. > > #1. Inline Assembly > > > > Code: > > register struct thread_info

Hello everybody, I'm curious whether there have been any attempts to perform performance analysis on the LLVA level. I am interested in the derivation of flow-facts (loop bounds etc. - what about the value-range-propagation pass I read about on this list some time ago) but even more I am interested in exec-time modeling (how long does it take to execute a bunch of LLVA instructions on

On 4/2/07, Fabian Scheler <fabian.scheler at gmail.com> wrote: > Hello everybody, > > I'm curious whether there have been any attempts to perform > performance analysis on the LLVA level. I am interested in the > derivation of flow-facts (loop bounds etc. - what about the > value-range-propagation pass I read about on this list some time ago) > but even more I am

On 7/19/13 3:20 AM, Herbei Dacian wrote: > > > Hi All, > can anyone tell me where I can find the sources for the llva-emu project? The llva-emu code is extremely old and, as I recall, not very feature-filled. It was also done for a class project (I don't think it was used for the original LLVA publication, and it wasn't used for any of the subsequent LLVA/SVA publications

Hi All, can anyone tell me where I can find the sources for the llva-emu project? I've tried to contact  Michael Brukman or Brian Gaeke but no reply. thank you for any help, dacian -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130719/94fcf74b/attachment.html>

> > LLVA specifically is refering to a research project offshoot of llvm. > > LLVM instructions do not have 1:1 mappings to native instructions > > (sometimes multiple llvm instructions map to fewer native insts, > > sometimes the other way around). > > That's correct, and furthermore, LLVA (now called SVA = Secure > Virtual Architecture) uses essentially the