similar to: [LLVMdev] anybody working on ARM Cortex support?

On Dec 18, 2008, at 7:05 PM, Sandeep Patel wrote: > Since there have been no answers, I will have to start at the > beginning. > > One of the first changes I'd like to try is adding the additional > registers and the AAPCS VFP variant calling conventions. Is there a > reason why the ARM Target isn't using the CCState machinery? Please clarify. I am not sure what you

Since there have been no answers, I will have to start at the beginning. One of the first changes I'd like to try is adding the additional registers and the AAPCS VFP variant calling conventions. Is there a reason why the ARM Target isn't using the CCState machinery? Deep On Fri, Dec 5, 2008 at 5:22 PM, Sandeep Patel <deeppatel1987 at gmail.com> wrote: > > Is anybody

Attached is a prototype patch that uses CCState to lower RET nodes in the ARM target. Lowering CALL nodes will come later. This patch does not handle f64 and i64 types. For these types, it would be ideal to request the conversions below: def RetCC_ARM_APCS : CallingConv<[ CCIfType<[f32], CCBitConvertToType<i32>>, CCIfType<[f64], CCBitConvertToType<i64>>,

Forgot to reply all to include the list. deep ---------- Forwarded message ---------- From: Sandeep Patel <deeppatel1987 at gmail.com> Date: 2010/11/17 Subject: Re: [LLVMdev] Build Attributes Proposal To: Rafael Espíndola <rafael.espindola at gmail.com> 2010/11/17 Rafael Espíndola <rafael.espindola at gmail.com>: >> Another use for build attributes would be as a means

Hi Sandeep, On 17 September 2010 18:52, Sandeep Patel <deeppatel1987 at gmail.com> wrote: > * Only these few renamed libcalls are set as AAPCS because other > libcalls may still want to be AAPCS-VFP. Even the F32 ones? Anton, As discussed, we might better put the FP helpers first, then deal with the REM and Memset later. If Sandeep's patch passes all tests, you can apply that

Dear all, I just sent a patch to llvm-commits about ARM RT-EABI support when choosing "arm/thumb*-eabi-*" triple. It involves three changes described in the path: 1. Floating point helpers (instead of GNU ones). This is supported by GCC as well, in EABI mode. 2. Reminder lowering, using ABI helper too. 3. Memset, changing the order of arguments, as required by the ABI. Please

Attached is an earlier patch I've been sitting on for clearly way too long. There are a few differences worth discussing: * Only these few renamed libcalls are set as AAPCS because other libcalls may still want to be AAPCS-VFP. * I have all the comparison CCs backward from you. I don't know offhand which is correct. * I put in the long long libcalls as well. Any or all of these

On 17 November 2010 23:13, Sandeep Patel <deeppatel1987 at gmail.com> wrote: > I suppose per-function is best. I'd argue that the ARM attributes are > all per-function as well. My favorite example is > __attribute__((pcs("aapcs-vfp"))) as a function attribute to select > the calling convention. > > Maybe these attributes could referenced like metadata so they

On Mon, Sep 27, 2010 at 5:02 PM, Evzen Muller <evzen.muller at arm.com> wrote: > > To make it easier to review & commit I have split and cleaned-up our > original > "Support for ARM Run-Time ABI" patch, this part adds support for calls which > > can be mapped using setLibcallName. As noted in the earlier thread on this, I'm pretty sure that we need to

> Hi Duncan, > > This could work, but it's very limited. Besides, there's already an MC > build attribute infrastructure, one would have to interpret those > strings in the back-end to an MC construct then back again to ASM and > ELF. > > I don't see why having a magic global would be worse than using module asm... So, you mentioned that there should be no

On May 9, 2011, at 1:41 PM, Renato Golin wrote: [snip] > One example is the struct byval. The ARM back-end still doesn't > support struct byval (maybe now it does, I was away for a while), The ARM backend now supports struct byval for APCS. Extending it to support AAPCS shouldn't be too difficult. Alas, I won't have time to revisit this in the near future. stuart

On Wed, May 11, 2011 at 11:42 PM, Stuart Hastings <stuart at apple.com> wrote: > > On May 9, 2011, at 1:41 PM, Renato Golin wrote: > > [snip] > >> One example is the struct byval. The ARM back-end still doesn't >> support struct byval (maybe now it does, I was away for a while), > > The ARM backend now supports struct byval for APCS.  Extending it to

I'm not currently setup to be able to run the A/B comparison tests that test-suite relies upon. Fhourstones-3.1 looks to be the simplest. If you can send me the two .o files from either EABI or Darwin, I can dig into why this went wrong for you. deep On Thu, Feb 26, 2009 at 3:53 PM, Evan Cheng <echeng at apple.com> wrote: > Sorry I haven't gotten back to you earlier. I have

After wasting an inordinate amount of time trying to get test-suite to run on arm-apple-darwin so I could reproduce your results, attached is a patch that fixes the small copy&paste error of having 8-byte alignment for stack-allocated f64s instead of the proper 4-byte. I've updated the patch to the top of trunk changes as well. deep On Fri, Feb 27, 2009 at 8:31 PM, Sandeep Patel

Hi, - Cortex-A8 needs a specific instruction scheduler as dual issue forces you to interleave some instructions to allow to run two instructions in the same cycle for the best performance (Cortex-A9 is out-of-order so dual issue is not an issue (!) for performance). - Cortex-A8/A9 have several useful new instructions : for instance, bit operations like bitfield insertion/extraction or having

This time with the test cases actually attached. deep On Tue, Feb 17, 2009 at 4:41 PM, Sandeep Patel <deeppatel1987 at gmail.com> wrote: > On Mon, Feb 16, 2009 at 11:00 AM, Evan Cheng <evan.cheng at apple.com> wrote: >> /// Information about how the value is assigned. >> - LocInfo HTP : 7; >> + LocInfo HTP : 6; >> >> Do you know why this change

Thanks. More questions :-) /// Information about how the value is assigned. - LocInfo HTP : 7; + LocInfo HTP : 6; Do you know why this change is needed? Are we running out of bits? - NeededStackSize = 4; - break; - case MVT::i64: - case MVT::f64: - if (firstGPR < 3) - NeededGPRs = 2; - else if (firstGPR == 3) { - NeededGPRs = 1; - NeededStackSize = 4; -

On 18 December 2013 09:42, Tim Northover <t.p.northover at gmail.com> wrote: > That means one strictly newer than > cortex-a8: cortex-a7 (don't ask), cortex-a9, cortex-a12, cortex-a15 or > krait I believe. > Hi Tim, Cortex A8 and A9 use VFPv3. A7, A12 and A15 use VFPv4. cheers, --renato -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Apr 16, 2009, at 2:52 AM, Sandeep Patel wrote: > After wasting an inordinate amount of time trying to get test-suite to > run on arm-apple-darwin so I could reproduce your results, attached is > a patch that fixes the small copy&paste error of having 8-byte > alignment for stack-allocated f64s instead of the proper 4-byte. I've > updated the patch to the top of trunk

On Mon, Feb 16, 2009 at 11:00 AM, Evan Cheng <evan.cheng at apple.com> wrote: > /// Information about how the value is assigned. > - LocInfo HTP : 7; > + LocInfo HTP : 6; > > Do you know why this change is needed? Are we running out of bits? HTP was't using all of these bits. I needed the hasCustom bit to come from somewhere unless we wanted to grow this struct, so I