similar to: [LLVMdev] Patch for WritingAnLLVMBackend.html

Hi LLVM developers, As one of the maintainers of AVR target, I want to update WritingAnLLVMBackend document to be familiar with the development of backend, because: 1. The structure of LLVMTargetMachine https://github.com/llvm-mirror/llvm/blob/master/docs/WritingAnLLVMBackend.rst#target-machine has been changed a lot! 2. LLVMInitializeSparcTargetInfo

On 7/13/2020 21:30, Thomas Lively via llvm-dev wrote: > Part of the problem is that ISel patterns are like their own DSL inside > the TableGen DSL, so keywords like "ins", "outs", and "ops" aren't > keywords at the TableGen level, but rather at the level of the ISel > system implemented with TableGen. Copying existing patterns and reading > the

Hi, We have some DSP architectures (kalimba) which have 24-bits as their "minimum addressable unit". So this means that the sizeof a char (and an int and a short for that matter) is 24-bits. I quickly read the posted link WritingAnLLVMBackend.html but did not see an obvious answer to the following question: Is it possible to write a backend that faithfully represents these

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello devs, I'd like to ask for some advise about adding a backend. I followed the steps at http://llvm.org/docs/WritingAnLLVMBackend.html (also adding the backend to the configure script, so it compiles (on Linux) with LLVM 3.1. However, llvm-build fails with: llvm[0]: Constructing LLVMBuild project information. Usage: llvm-build [options]

Thank You. On Fri, Jul 7, 2017 at 10:03 AM, Craig Topper <craig.topper at gmail.com> wrote: > Yes, that error is from instruction selection. I think your legalization > changes worked fine. > > ~Craig > > On Thu, Jul 6, 2017 at 8:21 PM, hameeza ahmed via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> also i further run the following command;

In attempting to add a backend I came across the documentation here: http://llvm.org/docs/WritingAnLLVMBackend.html The section on the build system seems to be out of date, or maybe I don't understand it. I copied the Sparc target to a directory (Foo for the example), added Foo to the subdirectories list in llvm\lib\Target\LLVMBuild.txt and to LLVM_ALL_TARGETS in llvm\CMakeLists.txt. I

Hello all, I am a beginner of LLVM and want to add a new Target for LLVM. I follow the document (http://llvm.org/docs/WritingAnLLVMBackend.html) to modify autotools/configure.ac. However when I type ./AutoRegen.sh There is an error that "Your autoconf was not detected as being 2.60" I download the source of autoconf 2.60 and install it. And there is the other error that "Your

I want to use LLVM as the main component in my compilation process. In doing so, I know I need to convert a high-level language to another language (python or a custom syntax.) The architecture I'm targeting is non-traditional hardware: microfluidic devices. Microfluidic devices are a specific class of reconfigurable computing; which don't necessarily adhere to a traditional

Hi Johnny, Thanks for this - particularly the tip about cfe-dev. I'm currently trying to coerce lldb to debug these type of architectures (our current toolchain already outputs good dwarf info). However, I'm struggling since lldb has just assumes that the size of a byte is universally 8-bits. At some stage, I *think* at some stage we'd like to derive a compiler, from the "same

Yes, llvm::InitializeAllTargetMCs(void) does seem to be autogenerated. It is _LLVMInitializeFooTargetMC that I can't find documented anywhere. On Sat, Mar 14, 2015 at 12:05 AM, Anton Korobeynikov < anton at korobeynikov.info> wrote: > This function is autogenerated. You need also to change top-level > configure / cmake files. > > On Sat, Mar 14, 2015 at 8:38 AM, Daniel

Dear all, I use the clang frontend to produce the control flow graph of a C program through this command: clang -Xclang -analyze -Xclang -analyzer-checker=debug.DumpCFG test.c The produced information contains all the basic blocks identified by labels, e.g. B1, B2, etc. along with their predecessors and successors. Is there a way to get the starting address of each of these basic block? I would

On Sun, Apr 24, 2005 at 07:15:03PM +0800, Tzu-Chien Chiu wrote: > i'd like to know if there is any plan or existing work to add a Aho's > trig language like code generator generator? I'm not aware of either the trig language code generator nor any work to implement it in LLVM. > "...If you are starting a new port, we recommend that you write the > instruction

On Feb 22, 2009, at 5:43 PM, Wesley J. Landaker wrote: > > I would love to see a Kalescope-like tutorial that goes step-by-step > through > making a backend. At the very least, I'll be documenting my > adventure, so > maybe once I know what I'm doing I can turn it into a tutorial. Have you seen: http://llvm.org/docs/WritingAnLLVMBackend.html If you're targeting

Hello, I am trying to find out where the complete documentation for the TargetDescription string documentation is. I am reading the tutorial and looking at the sparc backend at the same time and there are some discrepancies. Therefore the documentation would be extremely valuable but I can't seem to find it. In the tutorial it shows the string "E-p:32:32-f128:128:128", but the real

Hello > I'd like to ask for some advise about adding a backend. I followed > the steps at http://llvm.org/docs/WritingAnLLVMBackend.html (also > adding the backend to the configure script, so it compiles (on Linux) > with LLVM 3.1. This document is heavily out of date (so, I think it should be removed / marked obsolete). You might grab some information from

> In addition to thanking you for providing the info, I'm writing in the > hopes that there is some documentation that exists or that someone is > willing to add to http://llvm.org/docs/ExceptionHandling.html (or a more > appropriate place with a link there) that would cover the back end > (target-specific) aspects of EH. Perhaps just a quick description of what a > target

Hi Patrik, Thanks for this note. It's encouraging to read there has been some provision made for non-8-bit bytes. I'm not a compiler/backend expert, (although maybe I'll need to be soon!), so I won't look at the patches right now, however may at some stage in the future myself or colleague may request these patches from yourself. Yes, our 24-bit architectures have non-power-of-2

Hi, I'm developing a very basic new LLVM backend for a RISC machine (named Risco), based on the existing Sparc and Mips backends and the main tutorial [1]. I'm having trouble registering the backend so the main tools can see it. My project code is outside the source tree, and I've altered the Makefile to generate a shared library for the backend (libLLVMRiscoCodeGen.so). I've

I'm having a go at writing an LLVM backend for the WDC 65816. The documentation page on writing an LLVM backend<http://llvm.org/docs/WritingAnLLVMBackend.html>gives this example of target registration: extern "C" void LLVMInitializeSparcTargetInfo() { RegisterTarget<Triple::sparc, /*HasJIT=*/false> X(TheSparcTarget, "sparc",

I will take a look into NVPTX. I don't want to deconstruct C++ classes to generate Python code - I want to generate Python backend :) Its purpose is to be able to generate Python code from LLVM IR code (not C++ code! - C++ code is needed for me only to get a sample IR code). I want to write my custom compiler in the future and I want to be able to output Python code from it (of course not