similar to: [LLVMdev] ARM libgcc dependencies

I'm trying to implement something similar to this: http://gcc.gnu.org/wiki/SplitStacks in LLVM. The reason I want this is so that I can have dynamically growing and shrinking stacks in my programming language. In order to do this, I need to be able to check for overflow of a stack frame. The methods of doing this are outlined in the link above, but my intention is to pass the current stack

On Wed, Apr 7, 2010 at 12:43 PM, Arlen Cox <arlencox at gmail.com> wrote: > I'm trying to implement something similar to this: > http://gcc.gnu.org/wiki/SplitStacks in LLVM.  The reason I want this > is so that I can have dynamically growing and shrinking stacks in my > programming language.  In order to do this, I need to be able to check > for overflow of a stack frame.

I'm attempting to add an error handler to functions with a custom calling convention. This error is checked upon function entry, before any code is run (specifically, I cannot allow any stack operations). Because of this, I figured a good place to do this code insertion is in EmitPrologue. I also, at this time, create the block that handles the error case. // create a new block for

Hello, I think the current implementation for the call "bl __aeabi_idiv0" in builtins\arm\udivsi3.S is broken. At least for the case that __aeabi_idiv0 returns. (the provided implementation does) Since LR is not preserved, the following JMP(lr) results in an endless loop. Or is this an intentional change of the behavior? The file contains another implementation enabled by

samba server 2.0.6 DAVE 2.1 DAVE 2.0 When the DAVE 2.1 client tries to connect with samba, it gets an error that machine name doesn't match. This DAVE client connects with NT systems fine, and other Windows systems connect with samba fine, so it's just samba and DAVE that are having this failure to communicate. When DAVE 2.0 client tries, it connects fine but when I try to copy a file to

Yes, it's a bug. Please review https://reviews.llvm.org/D31716 On 4/5/2017 3:50 AM, Renato Golin wrote: > On 21 March 2017 at 18:32, Peter Jakubek via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> I think the current implementation for the call "bl __aeabi_idiv0" in >> builtins\arm\udivsi3.S is broken. >> At least for the case that __aeabi_idiv0

Dear List, I've been working with Asterisk CVS-v1-0-09 and i'm trying to enable attended transfer feature. but i just can't do it work. I've already set "atxfer = *" (and many other combinations) and all extensions on extensions.conf have the t and T option. But when I'm going to test, it doesn't work. Is there any other file that i have to configure in order to

Dear ML, Anton, Thank you for your answer and your help. I had a look at ARM.td of LLVM 2.6 (in lib/Target/ARM..) where I found following definitions: // V4T Processors. def : ProcNoItin<"arm7tdmi", [ArchV4T]>; def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>; def : ProcNoItin<"arm710t", [ArchV4T]>; def :

Hi, There are several places in compiler-rt which refer to __aeabi_idiv0. For example, in lib/builtins/arm/udivsi3.S: #ifdef __ARM_EABI__ b __aeabi_idiv0 #else JMP(lr) #endif At the same time there is no definition of it. It looks as if it was done intentionally so that third-party could provide custom handler for division by zero. IMHO It's not very consistent and looks odd as

I do 'make pridump' from the libpri source directory and receive the following: # make pridump cc -o pridump pridump.o -L. -lpri -lzap -Wall -Werror -Wstrict-prototypes -Wmissing-prototypes -g /usr/bin/ld: cannot find -lzap collect2: ld returned 1 exit status make: *** [pridump] Error 1 I am new to all of this, so I am sure I am missing something obvious, any help will be appreciated.

Dear Anton, Thank you again for your help! I tried with the following options (adding --with-cpu=arm7tdmi and using binutils from cvs snapshot): ../llvm-gcc4.2-2.6.source/configure --prefix=/usr/local/cross-llvm-gcc-arm-elf-4.2-2.6 --program-prefix=llvm- --enable-llvm=/Users/dummy/Develop/llvm/llvm-build --enable-languages=c,c++ --host=i686-apple-darwin9 --build=i686-apple-darwin9

Hello everyone, this is most likely Arm specific, but could affect other targets where there is a somewhat complex relationship between the triple and mcpu option. At present when clang is used as a linker driver for the gold-plugin and when using and an explicit -mcpu is not given to clang, then clang will always generate a -Wl,-plugin-opt=mcpu=<default CPU> where the default CPU is based

On 3/15/2018 9:43 AM, Peter Smith via llvm-dev wrote: > Hello everyone, this is most likely Arm specific, but could affect > other targets where there is a somewhat complex relationship between > the triple and mcpu option. > > At present when clang is used as a linker driver for the gold-plugin > and when using and an explicit -mcpu is not given to clang, then clang > will

Hello, Pazzo > Any clue? Yes. Sorry, my fault - next time I should check ARM docs before replying. ARM7TDMI is ARMv4T and this is not supported by LLVM (LLVM does v5+ codegen). -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

Hello, I am interested to use Speex but need to know If I can use it under our project's constraint. We need to use a low cost micro controller on a very small PCB. This means there's no space for an external DSP unit. Can someone tell me if using an AVR32 (Atmel uc) which has a floating point calculation unit and DSP instruction set and running at ~50Mhz for a narrow band

Hello, Pazzo > I had a look to llvm (2.6) configure options but I couldn't find any > way to specify cpu type, fpu ecc.. These are not llvm configure options, but gcc's one. Basically, you should configure llvm-gcc in the same way you do for gcc for your platform. > Could you please give me any > indication and/or example? I want to try llvm with Atmel's > AT91SAM7X256

Well, it's an ARM7TDMI core, so basically one register operation per clock, with memory accesses taking longer. Having the memory on-chip should make memory access much less of an impact. I was afraid that you would answer the way you did: I thought about my question after I sent it, and the "LP" in CELP is what makes it a sequential process; it can't do linear prediction on a

Dear Anton, Thanks for your help! I had a look to llvm (2.6) configure options but I couldn't find any way to specify cpu type, fpu ecc..Could you please give me any indication and/or example? I want to try llvm with Atmel's AT91SAM7X256 (core is ARM7TDMI ) Thank you again, pz 2010/1/9 Anton Korobeynikov <anton at korobeynikov.info>: > Hello > >> But I got the

Hello All. Could anybody help me with one question about CELT? I develop one project based on ARM7TDMI or Cortex C3 core. Can i use CELT with 32kHz and 48kB on these fixed point cores? Or it`s need to transfer project to Blackfin core (but it isn`t convenient to me)? With best regards, Alexey Voroshen.

I have to define a project that will have speex in the future. Can someone give me information about Speex running on an ARM7TDMI(v4) such as AT91SAM7S64? I will expect to use AEC, AGC noise reduction, encode and decode. Is this supposed to run? Or do I need something faster or different? Just for information: the chip runs at 55MHz, 1 wait stat in 32 bit mode or 0 wait in thumb mode. I