similar to: [LLVMdev] Custom lowering binary operations on one register machines.

On Nov 10, 2008, at 9:51 AM, sanjiv gupta wrote: > Ours is an accumulator based architecture. > > So one operand of ADD/SUB operations is in REG (accumulator) and the > other one is in Memory. The result can be left either in REG or > memory. > > The LLVM DAG for such operations expect both operands in REG. > > for example: > char a, b, c, d, e; > a = (b - c) +

Hi, Is it possible to add a spill code (a pair of store /load ) to the machinecode in a pass before the instruction emitter? If so, how can I calculate the address (offset to the sp) for the spill store/load instructions? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

For my target, I handle incoming memory arguments by creating a store to memory (in LowerCall, [1]), then creating a fixed object on the stack and loading from it (in LowerFormalArguments[2]). This approach was based on MSP430. I now have the problem that the resulting loads in my output assembly are done assuming that the call stack looks something like: ------ MemArg ------ MemArg ------

thanks Evan, I have just started writing td files. Any ideas how do I describe instructions for an accumulator based machine. The other pecularity is that we do not want to have any software stack. So the instructions like load and store have no meanings. In that case, how do I lower instructions that operate on stack frame? TIA, Sanjiv On 11/26/07, Evan Cheng <evan.cheng at apple.com>

Hello everybody, hi Evan, this patch changes the lowering of arguments for tail call optimized calls. Before arguments that could be overwritten by each other were explicitly lowered to a stack slot, not giving the register allocator a chance to optimize. Now a sequence of copyto/copyfrom virtual registers ensures that arguments are loaded in (virtual) registers before they are lowered to the

> On Feb 21, 2017, at 9:54 PM, Nemanja Ivanovic via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I believe that providing additional intrinsics that would directly produce the ISD::ADDC/ISD::SUBC nodes would provide the additional advantage of being able to directly produce these nodes for code that doesn't have anything to do with multiprecision addition/subtraction. I am

I'd think i1 would be the proper and correct choice for a carry flag for the generic instruction. I expect that would also make UADDO/USUBO redundant with ADDC/SUBC (which would seem a good outcome). You'd need to make sure the right thing happened when converting from ADDC's 1-bit carry in/out to X86ISD::AD[DC]'s EFLAGS i/o. Right now the conversion can get away with assuming

Hi, For some 64-bit immediates, ARM can generate a two instruction sequence. For example, for the following code: ; 734439407618 = 0x000000ab00000002 define i64 @f1(i64 %a) { %tmp = sub i64 %a, 734439407618 ret i64 %tmp } We should be able to generate: subs r0, r0, #1 sbc r1, r1, #171 @ 0xab But instead we get: $ llvm-as < %s | llc -march=thumb -mattr=+thumb2 mvn r2, #1

Could anybody guide me what information do I need to know about my target in order to provide the target lowering info to the llvm DAG generator? We do not have any fixed registers for argument passing. Everything including the formal and actual arguments will take part in a global interprocedural regalloc. Any pointers to learn about this will be a great help. Sanjiv

On Nov 24, 2007, at 7:28 PM, Sanjiv Gupta wrote: > Could anybody guide me what information do I need to know about my > target in order to provide the target lowering info to the llvm DAG > generator? We do not have any fixed registers for argument passing. > Everything including the formal and actual arguments will take part in > a global interprocedural regalloc. You don't

I've been playing around with llvm lately and I was wondering something about the bitcode instructions for basic arithmetic. Is there any plan to provide instructions that perform widening multiply, or add with carry? It might be written as: mulw i32 %lhs %rhs -> i64 ; widening multiply addw i32 %lhs %rhs -> i33 ; widening add addc i32 %lhs, i32 %rhs, i1 %c -> i33 ; add with carry

Hi, guys: I’m a developer of FydeOS. We porting ChromiumOS to amd64 and arm platforms. Now, I’m woking on porting android environment to Nvidia graphic cards. I have experience to port android to Vmware(SVGA). I found two display formats were not supported to display in nouveau driver: PIPE_FORMAT_R8G8B8A8_UNORM, PIPE_FORMAT_R8G8B8X8_UNORM. Which are defined at nv50/nv50_formats.c line: 130,131.

Hey, This was reported back in February and it seems nobody's given a shit? I've got a machine here with a Quadro 4000 that the screen locks up on every single time the monitor goes to sleep. Userspace is Ubuntu 16.04, kernel is recent mainline (4.12-rc4+). It's been happening since 4.10 though. Can we please see this fixed by 4.12? It's an enormous regression and a major hassle

https://bugs.freedesktop.org/show_bug.cgi?id=97462 Bug ID: 97462 Summary: Graphics deadlock "ILLEGAL_MTHD" in nouveau with mesa version 11.2.2 when visiting Google Maps with firefox 49.0b5 Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All)

https://bugs.freedesktop.org/show_bug.cgi?id=102430 Bug ID: 102430 Summary: nv4x - memory problems when starting graphical application - logs included Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium

Hi . For some time now i have had problems with video on this system . from dmesg iget the following 6.408406] nouveau [ DEVICE][0000:01:00.0] BOOT0 : 0x0a5000a2 [ 6.408411] nouveau [ DEVICE][0000:01:00.0] Chipset: GT216 (NVA5) [ 6.408414] nouveau [ DEVICE][0000:01:00.0] Family : NV50 [ 6.409206] nouveau [ VBIOS][0000:01:00.0] checking PRAMIN for image... [ 6.513939]

https://bugs.freedesktop.org/show_bug.cgi?id=99202 Bug ID: 99202 Summary: system freeze - fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT] - MULTIPLE_WARP_ERRORS - DATA_ERROR 00000004 [INVALID_VALUE] - ILLEGAL_CLASS ch 11 - RT_STORAGE_TYPE_MISMATCH - CLASS_SUBCH_MISMATCH Product: xorg Version: unspecified

Hi, Trying a new kernel on old [NV04] system I get tons of nouveau 0000:01:00.0: gr: intr 00000001 [NOTIFY] nsource 00000040 [ILLEGAL_MTHD] nstatus 00004000 [PROTECTION_FAULT] ch 0 [DRM] subc 3 class 004a mthd 02fc data 00000003 errors when operating on console. As I updated from 4.3 kernel, a bisect does not feel like the best start. What is that 02fc method which fbcon is probably

Hi, there! Every once in a while / about once a day I have nouveau for a Quadro NVS 290 failing in my system from about kernel 3.10...up to now 3.14, so I finally decided to report this bug as it gets really annoying. After the bug appears, there are some (one per DATA_ERROR line) small 20x20 to 40x40 pixel sized odd shaped white block artefacts stuck on my (dual monitor) desktop. After a restart

https://bugs.freedesktop.org/show_bug.cgi?id=91373 Bug ID: 91373 Summary: Nouveau fills kern.log with gigabytes of data when molecule screensaver is ran Product: xorg Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority: medium