similar to: [LLVMdev] What's does storeRegToAddr, loadRegFromAddr do?

On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote: > You need to specify sub-register == super-register, idx relationship. > See X86RegisterInfo.td: > > def x86_subreg_8bit : PatLeaf<(i32 1)>; > def x86_subreg_16bit : PatLeaf<(i32 2)>; > def x86_subreg_32bit : PatLeaf<(i32 3)>; > > def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, >

On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote: > > On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote: > > > What’s the value produced by an INSERT_SUBREG node? Is it a chain? > > > No, insert_subreg returns a value: > > > v1 = insert_subreg v2, v3, idx > > > v1 and v2 will have the same type, e.g. i16, and v3 must have a >

On Wed, 2008-10-15 at 10:08 -0700, Evan Cheng wrote: > On Oct 15, 2008, at 5:29 AM, sanjiv gupta wrote: > > > On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote: > >> You need to specify sub-register == super-register, idx relationship. > >> See X86RegisterInfo.td: > >> > >> def x86_subreg_8bit : PatLeaf<(i32 1)>; > >> def

In our case, storeRegToStackSlot, loadRegFromStackSlot clobbers some other physical register which may be holding a live value used somewhere else. How do I make regalloc aware so that it saves the value before storeRegToStackSlot and make it available again at the point of earlier use? TIA, Sanjiv -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Thu, 2008-10-23 at 11:17 -0700, Evan Cheng wrote: > > On Oct 22, 2008, at 11:09 AM, Sanjiv.Gupta at microchip.com wrote: > > > In our case, storeRegToStackSlot, loadRegFromStackSlot clobbers some > > other physical register which may be holding a live value used > > somewhere else. How do I make regalloc aware so that it saves the > > value before

On Oct 15, 2008, at 5:29 AM, sanjiv gupta wrote: > On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote: >> You need to specify sub-register == super-register, idx relationship. >> See X86RegisterInfo.td: >> >> def x86_subreg_8bit : PatLeaf<(i32 1)>; >> def x86_subreg_16bit : PatLeaf<(i32 2)>; >> def x86_subreg_32bit : PatLeaf<(i32

Pointer size on our target is 16-bits, and we have two 16-bit registers that can be used only to hold pointers (indirect addresses). All operations on the target are 8-bit operations, so it takes two 8-bit loads to load these pointer registers. We want LLVM to automatically expand all types to 8-bit values. The problem is that LLVM does not expand GlobalAddresses, which are 16-bit

You need to specify sub-register == super-register, idx relationship. See X86RegisterInfo.td: def x86_subreg_8bit : PatLeaf<(i32 1)>; def x86_subreg_16bit : PatLeaf<(i32 2)>; def x86_subreg_32bit : PatLeaf<(i32 3)>; def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], [AL, CL,

What's the value produced by an INSERT_SUBREG node? Is it a chain? Can I use to set a superreg of i16 type with two i8 values, and use the supperreg as an operand somewhere else? - Sanjiv -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20081002/f07bc88c/attachment.html>

On Oct 22, 2008, at 11:09 AM, Sanjiv.Gupta at microchip.com wrote: > In our case, storeRegToStackSlot, loadRegFromStackSlot clobbers some > other physical register which may be holding a live value used > somewhere else. How do I make regalloc aware so that it saves the > value before storeRegToStackSlot and make it available again at the > point of earlier use? >

On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote: > What’s the value produced by an INSERT_SUBREG node? Is it a chain? No, insert_subreg returns a value: v1 = insert_subreg v2, v3, idx v1 and v2 will have the same type, e.g. i16, and v3 must have a sub- register type, e.g. i8. > Can I use to set a superreg of i16 type with two i8 values, and use > the supperreg as

thanks Evan, I have just started writing td files. Any ideas how do I describe instructions for an accumulator based machine. The other pecularity is that we do not want to have any software stack. So the instructions like load and store have no meanings. In that case, how do I lower instructions that operate on stack frame? TIA, Sanjiv On 11/26/07, Evan Cheng <evan.cheng at apple.com>

def : Pat <(A), (B (C))>; can I connect B and C using a flag here? TIA, -Sanjiv

Is this something that will happen in future? Or there is no plan for it? Thanks, Ali -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Wednesday, April 02, 2008 10:30 AM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] Retrieving local variable names. It's not currently available. LLVM would have to

On Oct 15, 2008, at 11:21 AM, sanjiv gupta wrote: >>> >> >> Ok. The AX / AH super-reg and sub-reg relationship is not defined. In >> general x86 is not making good use of the high 8-bit sub-registers. >> We >> are leaving some performance on the table. We'll probably fix it one >> day. However, this doesn't apply to your target, right? There

Could anybody guide me what information do I need to know about my target in order to provide the target lowering info to the llvm DAG generator? We do not have any fixed registers for argument passing. Everything including the formal and actual arguments will take part in a global interprocedural regalloc. Any pointers to learn about this will be a great help. Sanjiv

On Nov 24, 2007, at 7:28 PM, Sanjiv Gupta wrote: > Could anybody guide me what information do I need to know about my > target in order to provide the target lowering info to the llvm DAG > generator? We do not have any fixed registers for argument passing. > Everything including the formal and actual arguments will take part in > a global interprocedural regalloc. You don't

On Thu, 2008-10-30 at 08:51 -0700, Evan Cheng wrote: > I think so. If you are defining your own SDNode's, you need to specify > one as producing a flag, i.e. SDNPOutFlag; the other will be reading a > flag, i.e. SDNPInFlag. > > Evan > The problem is that B produces two values: i8, flag. And I would like to connect C using the flag of B and not by i8. > On Oct 29,

I have two instructions , both have flag dependency onto a common instruction. So this forms a closed loop. The instruction scheduler asserts saying that the common instruction is already inserted into FlaggedNodes list....etc. Where can I get more info about the LLVM Instr scheduling pass? TIA, - Sanjiv

I think so. If you are defining your own SDNode's, you need to specify one as producing a flag, i.e. SDNPOutFlag; the other will be reading a flag, i.e. SDNPInFlag. Evan On Oct 29, 2008, at 2:55 AM, sanjiv gupta wrote: > def : Pat <(A), (B (C))>; > > can I connect B and C using a flag here? > > TIA, > -Sanjiv > _______________________________________________