Displaying 20 results from an estimated 400 matches similar to: "[LLVMdev] TableGen Hacking Help"
2008 Oct 20
0
[LLVMdev] TableGen Hacking Help
On Mon, 2008-10-20 at 11:49 -0500, David Greene wrote:
> I tried hacking tblgen to call getTargetNode / ReplaceUses if any node in the
> pattern has a chain by changing this line in tblgen:
>
> bool InputHasChain = isRoot &&
> NodeHasProperty(Pattern, SDNPHasChain, CGP);
>
> to call PatternHasProperty instead. This does cause tblgen to emit
>
2008 Oct 07
2
[LLVMdev] Making Sense of ISel DAG Output
On Friday 03 October 2008 12:06, Dan Gohman wrote:
> On Fri, October 3, 2008 9:10 am, David Greene wrote:
> > On Thursday 02 October 2008 19:32, Dan Gohman wrote:
> >> Looking at your dump() output above, it looks like the pre-selection
> >> loads have multiple uses, so even though you've managed to match a
> >> larger pattern that incorporates them, they
2008 Oct 07
0
[LLVMdev] Making Sense of ISel DAG Output
On Oct 7, 2008, at 12:04 PM, David Greene wrote:
> On Friday 03 October 2008 12:06, Dan Gohman wrote:
>> On Fri, October 3, 2008 9:10 am, David Greene wrote:
>>> On Thursday 02 October 2008 19:32, Dan Gohman wrote:
>>>> Looking at your dump() output above, it looks like the pre-
>>>> selection
>>>> loads have multiple uses, so even though
2008 Sep 12
3
[LLVMdev] Difficulty with reusing DAG nodes.
I'm trying to implement *MUL_LOHI for my processor.
My processor has mulxss (e.g.) that gives the 32 high bits of a 64 bit
multiply.
I tried this in ios2ISelDAGToDAG.cpp:
/// Mul/Div with two results
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI: {
SDValue Op1 = Node->getOperand(0);
SDValue Op2 = Node->getOperand(1);
AddToISelQueue(Op1);
2010 Feb 27
0
[LLVMdev] Possible SelectionDAG Bug
On Feb 26, 2010, at 2:07 PM, David Greene wrote:
> On Friday 26 February 2010 10:34:41 David Greene wrote:
>> On Friday 26 February 2010 09:55:32 David Greene wrote:
>>> In the continuing quest to try to track down problems we're seeing
>>> in
>>> SelectionDAG, I added the following assert
>>> toSelectionDAG::ReplaceAllUsesOfValuesWith:
>>
2008 Oct 03
0
[LLVMdev] Making Sense of ISel DAG Output
On Fri, October 3, 2008 9:10 am, David Greene wrote:
> On Thursday 02 October 2008 19:32, Dan Gohman wrote:
>
>> Looking at your dump() output above, it looks like the pre-selection
>> loads have multiple uses, so even though you've managed to match a
>> larger pattern that incorporates them, they still need to exist to
>> satisfy some other users.
>
> Yes,
2010 Mar 01
2
[LLVMdev] Possible SelectionDAG Bug
On Friday 26 February 2010 19:09:01 Dan Gohman wrote:
> I've now looked at your latest patch. In summary, it does expose a
> subtle problem. I haven't seen anything that here would lead to
> observable misbehavior yet though.
Well, I'm definitely observing misbehavior. I know it has something to do
with local changes here but I haven't isolated it yet.
>
2008 Oct 03
3
[LLVMdev] Making Sense of ISel DAG Output
On Thursday 02 October 2008 19:32, Dan Gohman wrote:
> Looking at your dump() output above, it looks like the pre-selection
> loads have multiple uses, so even though you've managed to match a
> larger pattern that incorporates them, they still need to exist to
> satisfy some other users.
Yes, I looked at that too. It looks like these other uses end up being
chains to
2008 Oct 02
0
[LLVMdev] Making Sense of ISel DAG Output
On Thursday 02 October 2008 11:37, David Greene wrote:
> I'll try ot write a small example and send it in a bit.
Ok, here's what I'm trying to do:
let AddedComplexity = 40 in {
def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:
$src1))),
(v2f64 (scalar_to_vector (loadf64 addr:
$src2))),
2010 Feb 26
2
[LLVMdev] Possible SelectionDAG Bug
On Friday 26 February 2010 10:34:41 David Greene wrote:
> On Friday 26 February 2010 09:55:32 David Greene wrote:
> > In the continuing quest to try to track down problems we're seeing in
> > SelectionDAG, I added the following assert
> > toSelectionDAG::ReplaceAllUsesOfValuesWith:
>
> Here's a patch to add more of these deleted node asserts. They fire
> tons
2010 Feb 22
4
[LLVMdev] SelectionDAG legality: isel creating cycles
I've run into a situation in isel where it seems like the selector is
generating a cycle in the DAG.
I have something like this:
0x215f140: v2f64 = llvm.x86.sse2.min.sd 0x215efd0, 0x21606d0, 0x215eb80
[0] 0x215efd0: i64 = Constant <647>
[0] 0x21606d0: v2f64 = scalar_to_vector 0x213b8f0
[0] 0x213b8f0: f64,ch = load 0x213b780, 0x213aa90, 0x213b610 <0x2113690:0>
alignment=8
2016 Jun 28
0
Question about changes to 'SelectionDAGISel.h'
"Martin J. O'Riordan" <martin.oriordan at movidius.com> writes:
> Thanks Ahmed and also Alex for your replies.
>
> This is more or less what I was realising, but it is a great
> confidence booster to know that it is the correct way also. I can
> replace all of my various 'Select*' specialisations with version that
> use
2009 Apr 13
1
[LLVMdev] Porting LLVM backend is no fun yet
Dan Gohman wrote:
> There certainly are wishlist items for TableGen and TableGen-based
> instruction descriptions, though I don't know of an official list.
> Offhand,
> a few things that come to mind are the ability to handle nodes with
> multiple results,
Is there an official workaround, BTW?
- Volodya
2017 Jul 29
2
ISelDAGToDAG breaks node ordering
Hi,
During instruction selection, I have the following code for certain LOAD
instructions:
const LoadSDNode *LD = cast<LoadSDNode>(N);
SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT,
PtrVT, MVT::Other,
LD->getBasePtr(), LD->getChain());
// Honestly, I have no idea what this does, but other memory
// accessing instructions
2017 Jul 31
0
ISelDAGToDAG breaks node ordering
On 7/29/2017 1:28 AM, Dr. ERDI Gergo via llvm-dev wrote:
> Hi,
>
> During instruction selection, I have the following code for certain
> LOAD instructions:
>
> const LoadSDNode *LD = cast<LoadSDNode>(N);
> SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N),
> VT, PtrVT, MVT::Other,
> LD->getBasePtr(), LD->getChain());
>
2008 Sep 11
0
[LLVMdev] Tail-calling
On Thu, Sep 11, 2008 at 4:31 PM, Arnold Schwaighofer
<arnold.schwaighofer at gmail.com> wrote:
> Tail calls through function pointers should work.If not please send a testcase.
>
> I just added the two examples from the bug (1392) that calls for true
> tail call support. They work on my machine (-tailcallopt needs to be
> enabled) ;)
>
> That would be commit 56127.
>
2015 Mar 09
2
[LLVMdev] LLVM Backend DAGToDAGISel INTRINSIC
I am currently working on DAGToDAGISel class for MIPS and am trying to
figure out a way to use INTRINSIC_W_CHAIN for an intrinsic which can return
a value.
My intrinsic is defined as:
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrReadWriteArgMem]>;
i.e. it has four arguments and one return value
In DAGToDAGISel when I try to pass it with four arguments and
2016 Jun 28
2
Question about changes to 'SelectionDAGISel.h'
Thanks Ahmed and also Alex for your replies.
This is more or less what I was realising, but it is a great confidence booster to know that it is the correct way also. I can replace all of my various 'Select*' specialisations with version that use 'ReplaceNode/SelectCode' and return 'void', but what about the places where I currently call 'Select(N)' directly?
2008 Sep 11
3
[LLVMdev] Tail-calling
Tail calls through function pointers should work.If not please send a testcase.
I just added the two examples from the bug (1392) that calls for true
tail call support. They work on my machine (-tailcallopt needs to be
enabled) ;)
That would be commit 56127.
regards
On Thu, Sep 11, 2008 at 11:21 PM, Evan Cheng <evan.cheng at apple.com> wrote:
> Arnold implemented tail call. We
2008 Sep 10
1
[LLVMdev] ReplaceUses: curious
Hi
I am looking at some of the existing targets to try to understand more
about writing a backend. I was a little puzzled by the use of a method
ReplaceUses in *ISelDAGToDAG.cpp (*= most targets, e.g. ARM, X86..).
I found its definition in the *GenDAGISel.inc file that is
autogenerated from the target description. I can only assume TableGen
emits this method definition for every traget.