similar to: [LLVMdev] Local common subexpression elimination

On Wed, 21 May 2008, Nicolas Capens wrote: > Thanks for the detailed explanations. I have a few remaining questions: > > Am I correct that ScalarReplAggregates is hardly more expensive than Mem2Reg > and therefore generally preferable? Right. > What would be the code quality implications of using "-dce -simplifycfg" > instead of -adce? As far as I understand the

Hi Chris, Thanks for the detailed explanations. I have a few remaining questions: Am I correct that ScalarReplAggregates is hardly more expensive than Mem2Reg and therefore generally preferable? What would be the code quality implications of using "-dce -simplifycfg" instead of -adce? As far as I understand the algorithms involved, -dce would hardly ever miss a dead instruction if

On May 20, 2008, at 8:57 AM, David Greene wrote: > On Tuesday 20 May 2008 07:03, Nicolas Capens wrote: > >> 1) Does ScalarReplAggregates totally superscede >> PromoteMemoryToRegister? I > > Nope, they are different. Mem2Reg is really important if you want > register > allocation. Actually SROA does fully subsume Mem2Reg. It iterates between breaking up

On Mon, 29 Jan 2007, Gil Dogon wrote: > Now the problem with this code , is that the calculation of the address > mat[i][j] which is done by the (two) getelementptr instructions > is quite expensive (involving at least two multiplications and one > addition) hence it actualy should have been moved out of the inner loop. Right. > and not twice. Anyway this is just a syptom of a

On Wednesday 21 May 2008 15:48, Chris Lattner wrote: > > What's the difference between GVN and GCSE, if they both perform common > > subexpression elimination? > > GVN does more, and is a better algorithm. GCSE is basically deprecated > and should be removed at some point. Er...waitaminute. Maybe there's something I don't fully grok about GVN, but in general,

Hello. I have a problem which is quite basic for array optimization, amd I wonder whether I am missing something, but I could not find the LLVM pass that does it. Consider the following code snippet: int test() { int mat[7][7][7]; int i,j,k,sum=0; for(i=0;i<7;i++){ for(j=0;j<7;j++){ for(k=0;k<7;k++){ sum+=mat[i][j][k]^mat[i][j][k^1]; } } } return

Hi Hal, Thanks for your comments! I'm inlining my responses below. Jingyue On Sat, Apr 19, 2014 at 6:38 AM, Hal Finkel <hfinkel at anl.gov> wrote: > Jingyue, > > I can't speak for the NVPTX backend, but I think this looks useful as an > (optional) target-independent pass. A few thoughts: > > - Running GVN tends to be pretty expensive; have you tried EarlyCSE

Hi, We wrote an optimization that eliminates common sub-expressions in a group of similar GEPs for the NVPTX backend. It speeds up some of our benchmarks by up to 20%, which convinces us to try to upstream it. Here's a brief description of why we wrote this optimization, what we did, and how we did it. Loops in CUDA programs are often extensively unrolled by programmers and compilers,

Hi all, I'm getting more impressed by LLVM day by day, but what's a bit unclear to me now is the order of optimization passes, and their performance. I think I have a pretty solid understanding of what each pass does at a high level, but I couldn't find any documentation about how they interact at a lower level. I'd like to use LLVM for generating high-performance stream

On Tuesday 20 May 2008 07:03, Nicolas Capens wrote: > 1) Does ScalarReplAggregates totally superscede PromoteMemoryToRegister? I Nope, they are different. Mem2Reg is really important if you want register allocation. > think I need it to optimize small arrays, but what is the expected added > complexity? I shouldn't think it would be very expensive at all. > 2) Does SCCP also

On Wed, Mar 7, 2012 at 12:47 PM, Nicolas Capens <nicolas.capens at gmail.com> wrote: > Hi all, > > I'm implementing a virtual processor which features dynamic register > indexing, and I'm struggling to make LLVM 3.0 produce good code for it. > The register set is implemented as an LLVM array so it can be > dynamically indexed using GEP. However, most of the time the

Hello, I'm writing for a backend and have a complicated instruction bundle (3 instructions) that has to be executed like a single block (meaning: if the first instruction is executed, all three have to be executed to obtain the result, though not necessarily without other instructions in between). Unfortunately, MachineCSE gets in the way sometimes and rips it apart. Is there a way to

I can't get the PERL subexpression translated to R. Following, for example, B. Ripley's http://finzi.psych.upenn.edu/R/Rhelp02a/archive/58984.html I am using sub, but it looks like an ugly substitute. Assume I want to extract the first alpha part and the first numeric part, but only if they are in sequence. Do I really have to use the sub twice, first extracting the first variable, then

I'm new to the LLVM, so please forgive what might be a silly question. I'd like to use the opt bytecode-to-bytecode optimizer, but when I try running it to do, for example, dead code elimination (-dce) or global common subexpression elimination (-gcse), nothing much seems to happen: opt -gcse -dce -o bar-opt.bc bar.bc llvm2cpp -o bar-opt.cpp bar-opt.bc

If an instruction is marked as side-effect free then it's a candidate for CSE. Try marking the instruction with hasSideEffects. Evan On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > Hello, > > I'm writing for a backend and have a complicated instruction bundle (3 > instructions) that has to be executed like a single block (meaning: if > the first instruction

Hi all, I'm implementing a virtual processor which features dynamic register indexing, and I'm struggling to make LLVM 3.0 produce good code for it. The register set is implemented as an LLVM array so it can be dynamically indexed using GEP. However, most of the time the virtual processor's registers are just statically indexed, and so I expected/hoped the code would be as

Hello again, Just wondering if there is a flag I can pass when compiling with llvm-gcc that can emit the llvm IR after the gvn pass (want to see the IR after dead code elimination/redundancy elimination). If so, will other passes be performed as well? I really just want to see the IR after the eliminations only, if it is at all possible. Thanks in advance, -nonpoly -- View this message in

Hello Jim. Just out of curiosity, won't such mechanism work via the patterns from instructions defs? Thanks. Girish. >________________________________ > From: Jim Grosbach <grosbach at apple.com> >To: Johannes Birgmeier <e0902998 at student.tuwien.ac.at> >Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Monday, 19 December 2011 10:33 PM

Hi Evan. The hasSideEffects method I believe operates only on Inline Assembly (IA) blocks. What if such a sequence is not part of IA? Thanks. Girish. If an instruction is marked as side-effect free then it's a candidate for CSE. Try marking the instruction with hasSideEffects. > >Evan > >On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > >> Hello, >>

Hi Johannes, You may be interested in the (very) recently added explicit instruction bundle support. For an example of their usage, have a look at the ARM backend's IT-block (Thumb2 predication support) pass, which uses them to tie instructions together. -Jim On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > Hello, > > I'm writing for a backend and have a complicated