similar to: [LLVMdev] sext..to instruction

On Mon, Oct 6, 2008 at 9:30 AM, Le Anh Quang <anh_quang.le at mailbox.tu-dresden.de> wrote: > Hi, > I have a question about the "sext..to" instruction. In the document, I found > two examples: > %x = sext i8 -1 to i16 > It means: > i8 -1 = 1111 1111 --> 1111 1111 1111 1111 = i16 > how can it determinate, that the i16 value %x positive is (65535)? > And

Hi, I have a question about the "sext..to" instruction. In the document, I found two examples: %x = sext i8 -1 to i16 It means: i8 -1 = 1111 1111 --> 1111 1111 1111 1111 = i16 how can it determinate, that the i16 value %x positive is (65535)? And the second example: %y = sext i1 true to i32 1 --> 1111 1111 1111 1111 1111 1111 1111 1111 In this example, %y is -1 I'm not sure

> I'm not sure about it, when sext to results a positve/negative value? sext does signed-extension, zext does unsigned-extension. This means that zext always extends by zero bits, while with sext the additional bits are all copies of the top bit of the original value. So with sext, if it was negative in the original type when considered as a signed value, then it will be negative in the

On Jun 20, 2013, at 4:39 PM, Bin Tzeng <bintzeng at gmail.com> wrote: > Hi all, > > There might be a simple error in the LLVM reference manual. The example for sext instruction: > > %X = sext i8 -1 to i16 ; yields i16 :65535 > > %X should yield i16: -1, as opposed to 65535. > Here is the simple patch (also attached): These are the same value. -Chris >

Hi all, There might be a simple error in the LLVM reference manual. The example for sext instruction: %X = sext i8 -1 to i16 ; yields i16 :65535 %X should yield i16: -1, as opposed to 65535. Here is the simple patch (also attached): Index: docs/LangRef.rst =================================================================== --- docs/LangRef.rst (revision 184496) +++ docs/LangRef.rst

Thanks for the reply. Just for a little more clarity, is i16, i32... signed, unsigned, or just a bit pattern? On Thu, Jun 20, 2013 at 9:17 PM, Chris Lattner <clattner at apple.com> wrote: > > On Jun 20, 2013, at 4:39 PM, Bin Tzeng <bintzeng at gmail.com> wrote: > > > Hi all, > > > > There might be a simple error in the LLVM reference manual. The example

Hi, This is somewhat similar to the previous thread regarding missed vectorization opportunities (http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-April/084765.html), but maybe different enough to require a new thread. I'm seeing some missed vectorization opportunities in the loop vectorizer because SCEV is not able to fold sext/zext expressions into recurrence expressions (AddRecExpr). This

I saw the description in llvm documenattion for sext is as the following : -- sext (CST to TYPE) Sign extend a constant to another type. The bit size of CST must be smaller or equal to the bit size of TYPE. Both types must be integers. But in the code of llvm-2.6, the judge condition just allow smaller to the bit size of TYPE as the following : case Instruction::SExt: return

Loads (on ptx64) with an sext of a computed index operand fail instruction selection: LLVM ERROR: Cannot select: 0x7ff01401c210: i64,ch = load 0x10580e820, 0x7ff01401b510, 0x7ff01401b910<LD4[%memref1], sext from i32> [ID=8] 0x7ff01401b510: i64 = PTXISD::LOAD_PARAM 0x10580e820, 0x7ff01401b410 [ORD=2] [ID=6] 0x7ff01401b910: i64 = undef [ORD=4] [ID=3] This is for code of the form: %ptr

For void test0(unsigned short a, unsigned short * in, unsigned short * out) { for (unsigned short w = 1; w < a - 1; w++) //this will never overflow out[w] = in[w+7] * 2; } I think it will be sufficient to add a couple of new cases to ScalarEvolution::HowManyLessThans -- zext(A) ult zext(B) == A ult B sext(A) slt sext(B) == A slt B Currently it bails out if it sees a non-add

In https://reviews.llvm.org/D68103 the InstCombine learned that shift-by-sext is simply a shift-by-zext. But the transform is limited to single-use sext. We can quite trivially get a case where there are two shifts by the same sext: https://godbolt.org/z/j6mO3t <- We should handle those cases. In https://reviews.llvm.org/D68103#1686130 Sanjay Patel notes that this sext is intrusive for

I'm working on a Z80 backend and am trying to efficiently lower SEXT, specifically 8 to 16 bit, in LowerOperation() according to the following rules: The Z80 has 8 bit registers and 16 bit registers, which are aliased versions of two 8 bit registers. 8 bit registers are named A, H, L, D, E and some more. 16 bit registers are HL (composed of H + L), DE (D + E) - and some more - with L and

Thanks for taking a look! On Tue, Oct 1, 2019 at 9:09 PM Philip Reames <listmail at philipreames.com> wrote: > On 9/27/19 1:40 PM, Roman Lebedev via llvm-dev wrote: > > In https://reviews.llvm.org/D68103 the InstCombine learned that shift-by-sext > > is simply a shift-by-zext. > > Just to make sure I'm following, the reasoning here is that the shift > amount must

Hi Devang, the improvements you made are good, I think the docs are a lot clearer now. I stil have a few more points, though. > > * The section "Functions" in the LangRef has a large textual description > > about how it should look, but no definition of syntax, or even a few > > examples of the syntax. This makes it very hard to read. > > This description

The thing is, we *don't* "not demand" those high bits. We *don't* not care what's in those bits - IR shifts don't mask their shift amounts. I.e we can't replace `x >> (32-y)` with `x >> (-y)`, which would be legal transform should we not demand those bits. We very much demand them. We just know those bits to be zero. And i'm not sure how to convey

I have a CopyToReg that is copying from different size types, what's the best way to change that to a zext or sext node based on signed or unsigned? I'm fairly unfamiliar with SelectionDAG process (outside of the docs on llvm website). It seems like I should be able to insert a custom hook using the register class to identify the type, potentially in ISelDAGToDag.cpp or is there a better

> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Bin Tzeng > Subject: Re: [LLVMdev] Error in the example of sext instruction in reference manual > Just for a little more clarity, is i16, i32... signed, unsigned, or > just a bit pattern? It's just a bit pattern. The operations performed on it can treat it as signed, unsigned, or

On Mon, Oct 7, 2019 at 11:32 AM Roman Lebedev <lebedev.ri at gmail.com> wrote: > > Bump. Any further thoughts here? > > To recap - i don't really see how this can be a demandedbits problem - we do > demand all those bits, we just know they must be zero. > (i would love to be proven wrong though!) > > Roman. > > On Tue, Oct 1, 2019 at 11:17 PM Roman Lebedev

I have a CopyToReg that is moving a 16bit reg to a 32bit reg, it's currently being mapped out as a simple mov (not an ext), I would like to change that to an ext. It seemed that the SelDAG was the easiest and cleanest way to do this. I can change the mov to an extension MI in the .td file; however, I can't tell at that point whether it's a sext or a zext, so it seemed the SelDAG was

Thanks for getting back to me. So those nodes record if the type has already been expanded from a narrower type. Can you elaborate how I could use these to help? Again, I'm pretty unfamiliar with the SDNodes. Thanks. On Tue, Jan 27, 2015 at 3:22 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote: > On 01/27/2015 12:16 PM, Ryan Taylor wrote: > > I have a CopyToReg that