similar to: [LLVMdev] sext..to instruction

> I'm not sure about it, when sext to results a positve/negative value? sext does signed-extension, zext does unsigned-extension. This means that zext always extends by zero bits, while with sext the additional bits are all copies of the top bit of the original value. So with sext, if it was negative in the original type when considered as a signed value, then it will be negative in the

On Mon, Oct 6, 2008 at 9:30 AM, Le Anh Quang <anh_quang.le at mailbox.tu-dresden.de> wrote: > Hi, > I have a question about the "sext..to" instruction. In the document, I found > two examples: > %x = sext i8 -1 to i16 > It means: > i8 -1 = 1111 1111 --> 1111 1111 1111 1111 = i16 > how can it determinate, that the i16 value %x positive is (65535)? > And

Hi, This is somewhat similar to the previous thread regarding missed vectorization opportunities (http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-April/084765.html), but maybe different enough to require a new thread. I'm seeing some missed vectorization opportunities in the loop vectorizer because SCEV is not able to fold sext/zext expressions into recurrence expressions (AddRecExpr). This

In https://reviews.llvm.org/D68103 the InstCombine learned that shift-by-sext is simply a shift-by-zext. But the transform is limited to single-use sext. We can quite trivially get a case where there are two shifts by the same sext: https://godbolt.org/z/j6mO3t <- We should handle those cases. In https://reviews.llvm.org/D68103#1686130 Sanjay Patel notes that this sext is intrusive for

For void test0(unsigned short a, unsigned short * in, unsigned short * out) { for (unsigned short w = 1; w < a - 1; w++) //this will never overflow out[w] = in[w+7] * 2; } I think it will be sufficient to add a couple of new cases to ScalarEvolution::HowManyLessThans -- zext(A) ult zext(B) == A ult B sext(A) slt sext(B) == A slt B Currently it bails out if it sees a non-add

Thanks for taking a look! On Tue, Oct 1, 2019 at 9:09 PM Philip Reames <listmail at philipreames.com> wrote: > On 9/27/19 1:40 PM, Roman Lebedev via llvm-dev wrote: > > In https://reviews.llvm.org/D68103 the InstCombine learned that shift-by-sext > > is simply a shift-by-zext. > > Just to make sure I'm following, the reasoning here is that the shift > amount must

The thing is, we *don't* "not demand" those high bits. We *don't* not care what's in those bits - IR shifts don't mask their shift amounts. I.e we can't replace `x >> (32-y)` with `x >> (-y)`, which would be legal transform should we not demand those bits. We very much demand them. We just know those bits to be zero. And i'm not sure how to convey

On Mon, Oct 7, 2019 at 11:32 AM Roman Lebedev <lebedev.ri at gmail.com> wrote: > > Bump. Any further thoughts here? > > To recap - i don't really see how this can be a demandedbits problem - we do > demand all those bits, we just know they must be zero. > (i would love to be proven wrong though!) > > Roman. > > On Tue, Oct 1, 2019 at 11:17 PM Roman Lebedev

I have a CopyToReg that is copying from different size types, what's the best way to change that to a zext or sext node based on signed or unsigned? I'm fairly unfamiliar with SelectionDAG process (outside of the docs on llvm website). It seems like I should be able to insert a custom hook using the register class to identify the type, potentially in ISelDAGToDag.cpp or is there a better

Thanks for getting back to me. So those nodes record if the type has already been expanded from a narrower type. Can you elaborate how I could use these to help? Again, I'm pretty unfamiliar with the SDNodes. Thanks. On Tue, Jan 27, 2015 at 3:22 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote: > On 01/27/2015 12:16 PM, Ryan Taylor wrote: > > I have a CopyToReg that

I have a CopyToReg that is moving a 16bit reg to a 32bit reg, it's currently being mapped out as a simple mov (not an ext), I would like to change that to an ext. It seemed that the SelDAG was the easiest and cleanest way to do this. I can change the mov to an extension MI in the .td file; however, I can't tell at that point whether it's a sext or a zext, so it seemed the SelDAG was

llvm-gcc is the C compiler, but you're trying to compile a C++ file. "@_Znwj" looks like part of a C++ symbol. Try llvm-g++ instead, that should help. - Simon 2008/7/23 Le Anh Quang <anh_quang.le at mailbox.tu-dresden.de>: > Hi, > I have tried to compile a simple cpp file with llvm-gcc. I have attached > the assemble file here. > I see a weird thing there.

Hi Alexandre, On Wed, Oct 19, 2016 at 6:27 PM, Alexandre Isoard <alexandre.isoard at gmail.com> wrote: > Really interesting read. I am perplexed now, and am not even sure what is > the meaning of undef anymore. Welcome aboard. :) > Example (unrelated to your blog post, but still weird): > %x = sext i1 undef to i2 > > I understand that I can replace it by either of: >

Hi Jean-Daniel, Thank I use VC++ 9 (express version). I have also an error in TableGen: The "strtoll" could not be found under win32. Have you fixed it ? Regards Quang -----Ursprüngliche Nachricht----- Von: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] Im Auftrag von Jean-Daniel Dupas Gesendet: Montag, 30. Juni 2008 22:00 An: LLVM Developers Mailing List

I'm working on a Z80 backend and am trying to efficiently lower SEXT, specifically 8 to 16 bit, in LowerOperation() according to the following rules: The Z80 has 8 bit registers and 16 bit registers, which are aliased versions of two 8 bit registers. 8 bit registers are named A, H, L, D, E and some more. 16 bit registers are HL (composed of H + L), DE (D + E) - and some more - with L and

Hi Jean-Daniel, thank for ur fast answer, i have fixed this error, another function was defined inside llvm source code. So, my only problem now is, I cannot create the file "configure.lib" (belongs to project "Configure"). I can build this project without error, but it didn't generate the lib data ?! Can you build this file ? if yes, I will be very happy if you send it to

Hi, I have tried to compile LLVM with Visual C++. Some subprojects work now. Other subprojects require the file "configure.lib". So I tried to compile the project "Configure". It could be built successfully, but the file "configure.lib" is not generated. So, what is the problem here ? Can somebody help me to fix that ? Thanks and regards Quang

Chris Lattner wrote: > On Nov 12, 2009, at 7:35 PM, Talin wrote: >> On Thu, Nov 12, 2009 at 5:58 PM, Chris Lattner <clattner at apple.com >> <mailto:clattner at apple.com>> wrote: >> >> >> There is also the issue of how constants should be represented. >> >> For all current processors that I know of, an intptr will be either >> 32 or

Hi Mehdi, On Wed, Oct 19, 2016 at 8:29 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: >> sext(x): >> t = zext x >> result = 0 >> for i = 0 to bitwidth: >> result |= t << i; >> return result > > I don’t understand this definition of sext? > Are you trying to express that we will copy the sign one bit at a time, and so every `new`

I have another round of questions about IR select canonicalizations. For the purity of this quiz, please disregard prior knowledge of how this is handled by instcombine or how this is lowered by your favorite target...of course we'll fix it. :) Some answers in the links below if you do want to know. Which, if any, of these is canonical? 1. Is a zext simpler than a select? a. define i32