similar to: [LLVMdev] PHI node generation

How do I determine what type of register(i.e. i32, f32, etc..) I am accessing from a MachineOperand? I.e. how do I get to the MVT struct, or equivalent information, from a MachineOperand object? Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596

Is there a way to tell LLVM to treat Boolean results as 32bit values instead of 1 bit values? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 -------------- next part -------------- An HTML attachment was scrubbed... URL:

I am attemping to figure out how to access the function names that are stored in a module so that I know which function I am currently in. I am attempting to write a backend that targets a language that only allows integer function names and I need to create mapping between the string and the integer. I've looked in the header files but I cannot determine how to extract the function

You can get to the MachineInstr from a MachineOperand. Then get to its TargetInstrDesc and TargetOperandInfo which has register class information. Evan On Sep 23, 2008, at 12:44 PM, Villmow, Micah wrote: > How do I determine what type of register(i.e. i32, f32, etc..) I am > accessing from a MachineOperand? I.e. how do I get to the MVT > struct, or equivalent information, from

I am having trouble trying to figure out two pieces of information from attempting to map arguments to registers. How do I determine, based on the argument name, which register the value is supposed to be assigned to? I can hard-coded it currently and it will be correct 100% of the time with the current set of assumptions, but I would rather determine it dynamically so that I can change my

Is there a known way to get pattern matching on the address space from tablegen? Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 -------------- next part -------------- An HTML attachment was scrubbed... URL:

I have a tablegen string that I want to add a modifier to the registers that are being matched. For example a simple match on fneg: def FNEG : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins GPR:$src0), "mov $dst, $src0", [(set GPR:$dst, (fneg GPR:$src0))]>; I want to place a modifier directly after $src0 in the string so that no space is between the string and

Is there a way for tablegen to generate patterns for all the data types of a specific register class instead of just the first one? Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 -------------- next part -------------- An HTML attachment was

When I setup my InstrFormat fields, I added some custom fields specific for my backend. How do I access these from inside LLVM? For example: class InstrFormat<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "AMD"; dag OutOperandList = outs; dag InOperandList = ins; let Pattern = pattern; let

A Function is a Value. See Value.h, look for getName(), etc. Evan On Sep 10, 2008, at 12:18 PM, Villmow, Micah wrote: > I am attemping to figure out how to access the function names that > are stored in a > module so that I know which function I am currently in. I am > attempting to write a > backend that targets a language that only allows integer function > names and I

Is there currently a way to have virtual register allocation information be saved across functions so that if I create a new virtual register in a function that it doesn't use a virtual register allocated in any previous function? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054

I am attempting to match setcc using tablegen w/ the following patterns: def FEQ : Instruction<(outs GPRF32:$dst), (ins GPRF32:$src0, GPRF32:$src1), "eq $dst, $src0, $src1", [(set GPRF32:$dst, (seteq GPRF32:$src0, GPRF32:$src1))]>; And it is failing stating that the result must be an integer. Is there a way around this other than modifying TargetSelectionDAG.td? Also,

On Nov 18, 2008, at 11:24 AM, Villmow, Micah wrote: > Is there a way to tell LLVM to treat Boolean results as 32bit values > instead of 1 bit values? LLVM IR doesn't have a concept of C level booleans. What problem are you trying to solve? -Chris > > Thanks, > > Micah Villmow > Systems Engineer > Advanced Technology & Performance > Advanced Micro Devices

I am not sure what you are looking to do. Please provide a mark up example. Evan On Oct 28, 2008, at 11:00 AM, Villmow, Micah wrote: > Is there currently a way to use a pattern inside of another pattern? > > Micah Villmow > Systems Engineer > Advanced Technology & Performance > Advanced Micro Devices Inc. > 4555 Great America Pkwy, > Santa Clara, CA. 95054 > P:

On Sep 25, 2008, at 10:49 AM, Villmow, Micah wrote: > I am having trouble trying to figure out two pieces of information > from attempting to map arguments to registers. > How do I determine, based on the argument name, which register the > value is supposed to be assigned to? > I can hard-coded it currently and it will be correct 100% of the > time with the current set of

That's how ISD::SETCC is specified. If you want to change that for your target, you should custom lower these nodes to target nodes. Then you can specify your own SDNode with your own SDTypeProfile. Evan On Oct 24, 2008, at 4:31 PM, Villmow, Micah wrote: > I am attempting to match setcc using tablegen w/ the following > patterns: > def FEQ : Instruction<(outs

On Sep 15, 2008, at 3:05 PM, Villmow, Micah wrote: > I am getting an assert on a bad legalization. > Assertion failed: Result.getValueType() == Op.getValueType() && "Bad > legalization!", file ..\..\lib\CodeGen\SelectionDAG\LegalizeDAG.cpp, > line 3976 > When you run into issues like this, it helps if you provide a bit more information. Please dump out

I am getting an assert on a bad legalization. Assertion failed: Result.getValueType() == Op.getValueType() && "Bad legalization!", file ..\..\lib\CodeGen\SelectionDAG\LegalizeDAG.cpp, line 3976 Can someone explain to me what this means in term of backend code generation, how it might be occurring, and possible ways to fix this? I don't see how the value type of an

No, there isn't something like that right now. What are you trying to accomplish? If you wish to implement this, it shouldn't be hard to do. Right now, MachineRegisterInfo re-starts virtual register number at TargetRegisterInfo::FirstVirtualRegister. You can add a mechanism to change that to a variable instead. Evan On Oct 20, 2008, at 1:43 PM, Villmow, Micah wrote: > Is

I am working on implementing break/continue and the flow control graphs that I am seeing are having all sorts of weird flow control that does not necessarily exist in the IR representation. For, example, a simple code segment that is a while loop w/ a continue ends up generating a CFG that is two while loops with one embedded inside each other. I've attached the dot files and the IR code. Any