similar to: [LLVMdev] Using VirtRegMap

On Sep 19, 2008, at 2:41 AM, Matt Elder wrote: > I'm trying to piece together a few assignments for a graduate-level > compilers class using LLVM; among these is a register allocator. I'd > like to provide a register allocator that, given a partially-allocated > VirtRegMap, will perform trivial register allocation (as in > RegAllocSimple) on the remaining, unmapped virtual

On Friday 19 September 2008 11:37, Evan Cheng wrote: > Please avoid using VirtRegMap. It's very tied to the current register > allocation pieces and not easily reusable. One of my mission in life > is to kill it. Im surprised to see this. I found it rather easy to re-use for custom register allocators. -Dave

Hi Susan, > But this doesn't seem to be happening; the stores to memory are there but > the loads are not. > > Any ideas what's going wrong? Are you using VirtRegMap::addSpillPoint and VirtRegMap::addRestorePoint ? If not you may need to add calls to them to let the rewriter know where to insert the loads/stores. > If not, any advice on how to generate the loads

On Tue, 23 May 2006, Vladimir Prus wrote: > right now, LLVM does register spilling by: > > 1. Creating stack object > 2. Passing index of that stack object to MRegisterInfo::storeRegToStackSlot > 3. At later stage, frame indices are replaced by calling to > MRegisterInfo::eliminateFrameIndex. > > This works for me, but there's slight problem. The target does not have

Hi, right now, LLVM does register spilling by: 1. Creating stack object 2. Passing index of that stack object to MRegisterInfo::storeRegToStackSlot 3. At later stage, frame indices are replaced by calling to MRegisterInfo::eliminateFrameIndex. This works for me, but there's slight problem. The target does not have "register + contant" addressing mode, so accessing frame index

On Wednesday 11 July 2007 15:07, Christopher Lamb wrote: > Could it be possible for there to be a harness type interface that > would allow coalescers that support both modes to be hooked into the > pass registration, and those that depend on the allocator not be > registered as passes? I have a patch for this kind of thing attached. Please take a look and let me know if it looks

Hi Evan, > Ok. Everyone has different idea about "easy". :-) I second your opinion that it is not very easy to use and it is very tightly coupled with the current linear scan register allocator implementation. > But VirtRegMap is going to be remove one of these days. When are you going to do that? Are you going to remove it from the source tree? Will it be replaced with

On Jul 11, 2007, at 11:39 AM, David Greene wrote: > On Wednesday 11 July 2007 12:41, Tanya M. Lattner wrote: > >> I think the coalescer should be flexible enough to be run >> independent of >> the register allocator. For example, you may want to expose the >> copies >> induced by transforming out of SSA to the scheduler. If the >> scheduler is

I found the problem! My generated code is spilling correctly but is not reloading at all. For example, if the original code has the equivalent of this (where %1024 is a virtual reg): %1024 = xxx ... yyy = %1024 and I find no physical register for %1024, then I assign it to physical register %edi and to a stackslot. That creates code like this: %edi = xxx store from %edi to the

> Hi Fernando, > > It's hard to say exactly what's happening because I don't know your > code (though, from the stack trace, it seems like there's some sort > of memory debacle), but looking at the comment in the > LiveVariableAnalysis.cpp file where it's folding memory operands, it > might explain somethings better: > > // Folding the

Hi, In the context of MachineCode custom inserter, I'm trying to enforce the mapping of virtual register to a physical one. According to the documentation https://llvm.org/docs/CodeGenerator.html#mapping-virtual-registers-to-physical-registers There are two ways: the direct one and the indirect ones. The indirect ones refer VirtRegMap class that I've never found. So I tried the direct

Hi again, After further investigation, I've found that the private PhysRegUseDefLists array ("head of use/def list for physical register") from MachineRegisterInfo class seems to be empty. But I didn't found any methods for updating such data structure. How/where this "use/def list" should be managed ? Is the documentation

Hey all, I've found a bug in either the PBQP register allocator or in VirtRegRewriter. I'm observing this assertion in VirtRegRewriter::rewrite() fail: unsigned VirtReg = MO.getReg(); unsigned PhysReg = VRM->getPhys(VirtReg); ... assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); Indeed there is a case where

Hi Chris, I saw this potential memory leak in RegAllocSimple.cpp. The PhysRegsEverUsed was being allocated but never freed. -bw Index: RegAllocSimple.cpp =================================================================== RCS file: /var/cvs/llvm/llvm/lib/CodeGen/RegAllocSimple.cpp,v retrieving revision 1.66 diff -a -u -r1.66 RegAllocSimple.cpp --- RegAllocSimple.cpp 22 Jan 2006 23:39:54 -0000

Hi Dominique, From your description it is not really clear what you are trying to do here. It may be the case that the goal you are trying to accomplish can be better reached using a different approach. In general, optimizations don't try to assign physical registers, that's done by the register allocation passes. There are some cases when target-specific passes use physical

I've been playing around with spillers and found that the SimpleSpiller fails badly on a particular code. The problem arises because SimpleSpiller does the test VRM.isAssignedReg(virtReg) which is implemented as: 00183 bool isAssignedReg(unsigned virtReg) const { 00184 if (getStackSlot(virtReg) == NO_STACK_SLOT && 00185 getReMatId(virtReg) == NO_STACK_SLOT)

Dear LLVMers, I am trying to fold memory operands in the way that is done in RegAllocLocal.cpp, or in LiveIntervalAnalysis.cpp, but I am getting errors that I don't know how to fix. Could someone tell me which steps should I take in order to correctly fold memory operands? The code that I am using is: const TargetMachine & target_machine = this->machine_function->getTarget();

I just updated from upstream llvm as of about last Thursday and I'm getting a segfault in VirtRegMap::RemoveMachineInstrFromMaps. It seems that the particular instruction being removed happens to reference an object at stack slot 4. The first spilled register is assigned stack slot 6 so LowSpillSlot == 6. Then, when we try to erase from SpillSlotToUsesMap, we index with a negative number.

Hi Krzysztof, Thanks for your response. I was trying to map function input parameters to machine specific registers. My solution I found is based to the RegInfo.setSimpleHint() API. Here is the body of the parameters loop of TargetLowering::LowerFormalArguments VReg = RegInfo.createVirtualRegister(RC); RegInfo.setSimpleHint(VReg,CLP::FA_ROFF1+i);

On May 8, 2008, at 11:36 AM, David Greene wrote: > I just updated from upstream llvm as of about last Thursday and I'm > getting a segfault in VirtRegMap::RemoveMachineInstrFromMaps. > It seems that the particular instruction being removed happens > to reference an object at stack slot 4. The first spilled register is > assigned stack slot 6 so LowSpillSlot == 6. Then, when