similar to: [LLVMdev] Custom Opcodes versus built-in opcodes

On Thu, Sep 18, 2008 at 4:04 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I am using lowering instructions and using custom opcodes that I can more > easily directly map to my backend. These opcodes are then used to emit a > custom set of instructions into the MachineBasicBlock. I've been able to get > one to work correctly, however, I've ran into an issue where

On Sep 18, 2008, at 4:04 PM, Villmow, Micah wrote: > I am using lowering instructions and using custom opcodes that I can > more easily directly map to my backend. These opcodes are then used > to emit a custom set of instructions into the MachineBasicBlock. > I’ve been able to get one to work correctly, however, I’ve ran into > an issue where my second one is being

________________________________ From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Chris Lattner Sent: Friday, September 19, 2008 10:49 AM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] Custom Opcodes versus built-in opcodes On Sep 18, 2008, at 4:04 PM, Villmow, Micah wrote: I am using lowering instructions and using custom opcodes that

On Sep 19, 2008, at 11:35 AM, Villmow, Micah wrote: > Make sure to use DAG.getTargetNode() with custom opcodes. "target" > nodes are encoded with an implicit delta added to their enum value. > > Is this documented anywhere that getTargetNode is the preferred > method to use in a Custom Lowering function? Even the other backends > use getNode in their lowering

Dan Gohman wrote: > There certainly are wishlist items for TableGen and TableGen-based > instruction descriptions, though I don't know of an official list. > Offhand, > a few things that come to mind are the ability to handle nodes with > multiple results, Is there an official workaround, BTW? - Volodya

You can tell LLVM that you have "sign extended" setCC results (all ones). Dan On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote: > On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah > <Micah.Villmow at amd.com> wrote: >> The IR produces correct results, but my backend does not and the >> only thing >> I can think of is that the IR is treating the

Ok, this is really complicated. I need some TableGen experts to help here. I need a little help doing a final bit of tblgen hacking. I've hacked tblgen to handle patterns like this: let AddedComplexity = 40 in { def : Pat<(vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:$src1))), (v2f64 (scalar_to_vector (loadf64 addr:$src2))),

I'm trying to implement *MUL_LOHI for my processor. My processor has mulxss (e.g.) that gives the 32 high bits of a 64 bit multiply. I tried this in ios2ISelDAGToDAG.cpp: /// Mul/Div with two results case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { SDValue Op1 = Node->getOperand(0); SDValue Op2 = Node->getOperand(1); AddToISelQueue(Op1);

On Thu, Sep 11, 2008 at 4:31 PM, Arnold Schwaighofer <arnold.schwaighofer at gmail.com> wrote: > Tail calls through function pointers should work.If not please send a testcase. > > I just added the two examples from the bug (1392) that calls for true > tail call support. They work on my machine (-tailcallopt needs to be > enabled) ;) > > That would be commit 56127. >

Tail calls through function pointers should work.If not please send a testcase. I just added the two examples from the bug (1392) that calls for true tail call support. They work on my machine (-tailcallopt needs to be enabled) ;) That would be commit 56127. regards On Thu, Sep 11, 2008 at 11:21 PM, Evan Cheng <evan.cheng at apple.com> wrote: > Arnold implemented tail call. We

Hi! I noticed in the LegalizeDAG.cpp (SelectionDAGLegalize::LegalizeOp): case ISD::INIT_TRAMPOLINE: case ISD::FRAMEADDR: case ISD::RETURNADDR: // These operations lie about being legal: when they claim to be legal, // they should actually be custom-lowered. Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); if (Action == TargetLowering::Legal)

On Fri, 12 Jan 2007, Nicolas Geoffray wrote: > I'm currently implementing a linux/ppc target in llvm. The abis between cool > Darwin/ppc and linux/ppc are different and I'm running into problems > with vararg calls. ok > Before a variadic method is called, an extra instruction must be > executed (which is creqv 6, 6, 6). This instruction is not necessary in >

Hi all, I'm currently implementing a linux/ppc target in llvm. The abis between Darwin/ppc and linux/ppc are different and I'm running into problems with vararg calls. Before a variadic method is called, an extra instruction must be executed (which is creqv 6, 6, 6). This instruction is not necessary in Darwin/ppc. I looked into the PowerPC target implementation and the code generation

On Nov 4, 2008, at 12:12 AM, Matthijs Kooijman wrote: > Hi Dan, > >> Having tblgen pretend that the MOVE isn't the root seems a bit >> counter-intuitive though. > I didn't really mean making RD the root, but rather telling tablegen > that RD > is the "primary" node, corresponding to the input pattern. This > would allow > the properties of

There are LLVM 2.9 RC1 pre-release tarballs source available. You can find them here: http://llvm.org/pre-releases/2.9/ Please download them, build them, and compile things to your heart's content. And most importantly file a bunch of bug reports. :-) Share and enjoy! -bw

Hi Dan, > Having tblgen pretend that the MOVE isn't the root seems a bit > counter-intuitive though. I didn't really mean making RD the root, but rather telling tablegen that RD is the "primary" node, corresponding to the input pattern. This would allow the properties of the input rd SDNode be properly transferred to the output RD node instead of the MOVE node. I doubt

Can someone explain how the condition code is passed from the MBlazeTargetLowering::LowerSELECT_CC to MBlazeTargetLowering::EmitCustomSelect custom inserter? In LowerSELECT_CC the condition code is never accessed (Op.GetOperand(4)) and I don't see how it ends up getting correctly passed to the MBlazeTargetLowering::EmitCustomSelect. > SDValue

Hi All, I'm sorry if this has come up before somewhere on the list, but: Is it possible to tag those opcodes in the llvm bitcode that a) require supervisor (Ring 0) priviledge, or b) cause a trap, e.g. INT or SYSCALL on x86? My reasoning for asking is that the new MCJIT is able to JIT embedded asm (containing such opcodes) but for implementing a sandboxed runtime environment it would

Hi Is there a way to associate additional info with every opcode like an id either through the td files or when building an instruction ? thanks shrey

On Aug 13, 2011, at 11:04 AM, shreyas krishnan wrote: > Hi > Is there a way to associate additional info with every opcode > like an id either through the td files or when building an instruction > ? > The only way I can think of is metadata on the LLVM IR instruction: http://llvm.org/docs/LangRef.html#metadata -bw