similar to: [LLVMdev] LLVM FPGA interface.

I'm using Markdown in an app and would like to provide support for including a table of contents. Any suggestions for a syntax? Has anyone done this before? My first thoughts are: 1. Have a special header item (using markdown extra's header syntax), e.g. generate-contents: yes 2. Have a special xml tag with optional alternative text inside, e.g. <contents> 1. First thingy 2.

Hello. Nice to meet you. My name is Seung Jae Lee, a graduate student in UIUC CEE, who is working in NCSA for the present. Nowadays I am trying to develop LLVM backend to spit out CHiMPS assembly code. In the process, I installed LLVM codes on my home directory in the host computer. But I don't think it was installed properly. While bootstrapping the LLVM C/C++ Front-End, I met several

Dear all, I was testing the wonderful package APE. However upon testing a particular Newick's format tree - which I think to be a non-binary tree - it yields different result as expected. > library(ape) > tree.hiv <- read.tree(text="(rat,mouse,(human,chimp));") > is.binary.tree(tree.hiv) [1] TRUE Was that a bug in APE package? - Gundala Viswanath Jakarta - Indonesia

Hi, It's unfortunate that with recent revisions of R 2.13 (this appeared in revision 54640, March 2), 'R CMD build' now removes empty dirs in the package. People might have good reasons for having empty dirs in their packages. For example, in Bioconductor, we have some tools to automatically generate annotation packages and those tools are implemented in software packages that use

Hi, Would anyone happen to know if there are any efforts underway at enhancing the Trident compiler? Some of the things that I would like to add to the Trident compiler are : a. Support for compiling multiple C functions in an input file b. Support for parameter passing c. Support for functions returning results d. Support for a C++ front end, and C++ objects e. Updating the trident

i've just lost $2000 dollars or so on my first commercial asterisk installation .. i'm running a PIV class server, three Digium Wildcard FXO cards, and 10 Grandstream Budgettone SIP phones. The system was to be a PBX for a small company. After over 2 months of pissing about, the client has had his fill of asterisk problems, and asked me to take my equipment out of the building. Obviously,

Here http://lists.xiph.org/pipermail/theora/2004-September/000619.html Andrey describe encoder structure, this like: "I see the following structure of the compressor implemented in the FPGA (Xilinx Spartan 3 1000K gates): 1. Data from the external frame buffer (FB) memory goes to the Bayer-to-YCbCr (4:2:0) converter in overlapping 20x20 tiles that produce 6 8x8 blocks (one macroblock) on the

Dear R users, my search for a possibility to convert a generated model into VHDL to program an FPGA has still no solution. The problem: caret -> training -> model -> model.rds -> model.xml (PMML) --?--> VHDL-Code --?--> FPGA The (simplified) task: A photo detector with 16 channels is measuring the intensity of 16 different wavelength ranges. These data are classified with the

I'm not aware of an FPGA implementations yet. You could be the first! An encoder implementation would be much easier, because there are almost no rules about encoders. An encoder is free to behave any way it wants, so you could implement a very small subset of Opus and still have a compliant (and useful) encoder. A decoder implementation would be much harder, because decoders are required

Hello people My name is Felipe and I sent a proposal to the Google Summer of Code that the goal is to get a FPGA embeded system decoding Theora Streams in real-time. It was accepted and the mentor is the Ralph Giles. The proposal can be viewd here: http://atlas.lsc.ic.unicamp.br/~portavales/wp-content/uploads/2006/05/soc_proposal.txt There is also a presentation with a better division of the

Good news, Working with synchrounous RAM (fpga internal SRAM blocks) the area usage drop from 20% to 5% of Logic Cells. And the clock frequency from 30 Mhz to 90 Mhz. Now I'm improving the latency of samples (number of clock cycles needed to decode a data sample). Report: -------------- Fitter Status : Successful - Mon Jun 5 16:38:21 2006 Quartus II Version : 5.1 Build 176 10/26/2005 SJ

Hi, I did some improvements and some bug corrections in Theora FPGA code. I'd like to post this new version in the SVN. How can I do that? Thanks -- Leonardo de Paula Rosa Piga Undergraduate Computer Engineering Student LSC - IC - UNICAMP http://www.students.ic.unicamp.br/~ra033956

Hi all, Great news. On Thursday I finally play a video on FPGA. As I said the implementation is using the NIOS II processor. Andr? Costa is hard working to use the LEON processor. The video resolution is 96x80, because we have some FPGA internal memory constraints. I will try to use external memory to make possible decode a video of at least 320x240. The result can be see here:

folks hi, something i just wanted to double-check. is it possible to use, with LLVM, entirely free software tools to build and upload to a xilinx microblaze FPGA target? i take some c code, put it through llvm-fpga, aaand... then what? is there any documentation about this stuff, anywhere? tia, l.

Hi, I'm not sure, but I think you should do point 'e' first - unless you want to implement 'a' to 'd' first for 1.5 and then again for 2.4. Best regards, Nico On Dec 29, 2008, at 1:44 PM, Elvis Dowson wrote: > Hi, > Would anyone happen to know if there are any efforts underway > at enhancing the Trident compiler? > > Some of the things that I

Great news! Theora is running on FPGA. After almost a year of a great effort we have Theora validated on FPGA. Now I will try to integrated the hardware with a video controller to see the video! I completely implemented the ExpandBlock, CopyRecon, LoopFilter and UpdateUMVBorder functions. The ReconRefFrames function was partially implemented and the part before will run on a software compiled

Hi, We would like to use the OPUS codec @ 16 kHz sampling rate and max 32 kbps. What about implementing an OPUS coder and decoder in an FPGA? Has this been done? Would either coder or decoder more suitable for FPGA implementation? Best regards Fredrik Bonde -------------- next part -------------- An HTML attachment was scrubbed... URL:

I'm considering implementing the Theora format in the FPGA of the new camera. The previous model (Elphel 313 - http://www.elphel.com, https://sourceforge.net/projects/elphel) had smaller FPGA and was able to produce just motion JPEG utilizing 97% of the resources. The new (model 333) camera uses 3 times bigger FPGA (and also faster), it also has increased frame buffer and system memory.

I'm considering implementing the Theora format in the FPGA of the new camera. The previous model (Elphel 313 - http://www.elphel.com, https://sourceforge.net/projects/elphel) had smaller FPGA and was able to produce just motion JPEG utilizing 97% of the resources. The new (model 333) camera uses 3 times bigger FPGA (and also faster), it also has increased frame buffer and system memory.

Just to make sure, what's the goal here? Is the goal 1) to have a fast Opus implementation or are you 2) looking for an interesting FPGA implementation project? If 1), then an FPGA is most likely not necessary since Opus is not computationally expensive. If 2), then it depends on the desired size of the project and the desired quality. The simplest encoder possible is indeed simpler than the