similar to: [LLVMdev] hard values in SequentialType::indexValid () method

On Aug 18, 2008, at 4:20 PM, Alireza.Moshtaghi at microchip.com wrote: > This method is defined in: > Lib/VMCore/Type.cpp > And it makes hard assumption that size of integer is 32 or 64. > This gives us trouble because we have 16 bit integer. > Is there a reason for this assumption? Or we can just add the 16-bit > integer to it as well? Hi Alireza, The reason for this is that

What is the reason for getelementptr being tied to only 32 or 64 bit indexes? It seems to me that integer size would be better choice... Anyways, this is getting in our way. What is your suggestion? Thanks Ali > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of Chris Lattner > Sent: Monday, August 18, 2008 4:33

> Two options: 1) change LLVM IR to allow it, or 2) just insert sign/ > zero extension instructions. > > Does this actually affect the code being generated in practice? Inserting sign/zero extension instructions actually do tend to increase the generated code pretty dramatically on our target. So I prefer option (1) Does this change have dramatic affect on LLVM IR? PS. Currently

> I realize that sign extensions have non-zero impact when they exist in > the .s file. My assertion is that these will be zapped by the dag > combiner. Have you actually tried this? Yes, I have and they work just fine for us. I misunderstood your first email, I thought you are pointing at a problem, while you are actually saying that there is no problem. So back to my original

On Aug 19, 2008, at 6:54 AM, Alireza.Moshtaghi at microchip.com wrote: > What is the reason for getelementptr being tied to only 32 or 64 bit > indexes? As usual, the answer is "that is all anyone has needed so far" :) > Anyways, this is getting in our way. What is your suggestion? Two options: 1) change LLVM IR to allow it, or 2) just insert sign/ zero extension

On Aug 19, 2008, at 4:14 PM, Alireza.Moshtaghi at microchip.com wrote: >> Two options: 1) change LLVM IR to allow it, or 2) just insert sign/ >> zero extension instructions. >> >> Does this actually affect the code being generated in practice? > > Inserting sign/zero extension instructions actually do tend to > increase > the generated code pretty

Some of the optimizations that the first DAG combine performs is counter productive for our 8-bit target. For example in: // I dropped the types because they are irrelevant. // Excuse me for changing the syntax... store %tmp1, %var %tmp2 = load %var %tmp4 = add %tmp3, %tmp2 Since load is the only user of var and since var has just be stored to, it assumes that %tmp1 is alive and it goes ahead

I can't think of any workaround? this optimization eliminates so much information that if we want to retrieve back, it will take a lot of processing and may not necessarily be able to retrieve the lost information for all cases. Besides, why does the generic part of llvm have to force an optimization that is counter productive to some targets? If there are other phases that do the same

I am trying to verify the generated DAG after converting from llvm to DAG, however I'm not sure if this is correct or not. Here is the situation: In order to get LLVM to lower to 8-bit I have to define only 8-bit registers and the pointer size also to be 8-bit. Doing so, the attached DAG is generated for a load:i16. I have problem understanding this DAG in two places: 1)As you can see the

Thank you Evan, I added the return Type::Int8Ty to the switch statement to get it to work. I don't know if this can have other consequences, I haven't yet verified if the generated Legalized DAG is correct though. A. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Monday, October 01, 2007 3:23 PM To:

Remember, our target does not have registers like ordinary processors do. So register allocation is really not going to do much for us. What we have to do is to exploit the existing opportunities in the source code and try to generate code based on such opportunities. The dag combination in question is one such opportunity that is being destroyed by the optimization. You maybe right in that this

I need to perform call graph analysis (after all modules are merged) to find which function calls which, and depending on the attributes that each function has and what functions call it, I may need to clone it and modify some of calls to that function to call the cloned function. Currently we are doing this in few acrobatic moves that span from an llvm-ld pass (to do call graph analysis) all the

Thank you Chris, That is great news... So his modifications are in llvm-2.2? How has Christopher tested them? Are there attributes or intrinsics that I can also use? A. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Chris Lattner Sent: Tuesday, January 29, 2008 9:23 PM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] C

Below I have pasted the latest design that we discussed... Now we would like to pick it up and do the implementation. 1) Is there any last change that we would like to add? 2) Has anyone been working on it? I haven't seen any thing new in the code so I assume the answer is no... Thanks Alireza Moshtaghi Senior Software Engineer Development Systems, Microchip Technology Subject: Troubling

The code sequence: > store %tmp1, var > > tmp4 = add %tmp3 , %tmp1 > can happen even if you eliminate the specific dag combine in question. The real solution lies elsewhere. To me, this seems more like a register allocation problem. Evan On Mar 22, 2009, at 9:39 PM, Alireza.Moshtaghi at microchip.com wrote: > I can't think of any workaround? this optimization eliminates

So does that mean that LLVM can't lower automatically to 8-bit values? I tried defining 8-bit pointers in the subtarget using "p:8:8:8" but it asserts at line 566 of TargetData.cpp in the default case of TargetData::getIntPtrType() Is it difficult to add 8-bit support? A. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On

Christopher, Thank you for all the work :-) Regarding the regression testing, it is in our plan to contribute into LLVM. The current state of our project is not in the form that we can do this at this time though, but I'm hoping that we can get some minimal functionality into LLVM before LLVM 2.3 (at most LLVM 2.4) release. Looks like you have also (at least on your local project) taken

Evan, The machine is 8 bit, and of course all registers are 8-bit too. Memory access on this machine is a bit different. The memory is banked into banks of 256-byte, and you can select the active bank using a bank select register. All instructions can access the memory with an 8-bit operand, so in that sense the address space can be viewed as 256-byte long. On the other hand, there are three

On Oct 8, 2007, at 3:15 PM, Alireza.Moshtaghi at microchip.com wrote: > I am trying to verify the generated DAG after converting from llvm to > DAG, however I'm not sure if this is correct or not. > Here is the situation: > In order to get LLVM to lower to 8-bit I have to define only 8-bit > registers and the pointer size also to be 8-bit. > Doing so, the attached DAG is

On Mon, 19 May 2008 Alireza.Moshtaghi at microchip.com wrote: > Correction: > > The analysis I made regarding the callers knowledge of sign/zero > extension of return value is flawed. So I take it back. > > Never the less, I don't see how adding attributes would resolve this > problem either. Ok, I'm not sure what issue you mean. Can you restate? -Chris >