similar to: [LLVMdev] Indirect Branch Representation

On Wed, Jul 23, 2008 at 5:57 PM, kapil anand <kapilanand2 at gmail.com> wrote: > Hi, > > I was thinking about the ways to represent indirect branch in LLVM. It seems > that "Switch instruction" is the only way to logically represent indirect > branch inside LLVM. > Is there any other easier way to represent indirect branch in LLVM? Yeah, that's essentially

Specifically, I need a way to represent indirect branch instruction (in binary) as an equivalent LLVM instruction. With switch instruction , I would have to list all the possible targets and then initialize the corresponding instruction. I was just thinking whether it might be possible to have some kind of indirect branch where label is a "variable" and not an explicit label present in

On Wed, Jul 23, 2008 at 8:47 PM, kapil anand <kapilanand2 at gmail.com> wrote: > > Specifically, I need a way to represent indirect branch instruction (in > binary) as an equivalent LLVM instruction. With switch instruction , I would > have to list all the possible targets and then initialize the corresponding > instruction. I was just thinking whether it might be possible to

Just to make sure, can the label in a branch instruction be a "variable"? On Thu, Jul 24, 2008 at 12:08 AM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Wed, Jul 23, 2008 at 8:47 PM, kapil anand <kapilanand2 at gmail.com> > wrote: > > > > Specifically, I need a way to represent indirect branch instruction (in > > binary) as an equivalent LLVM

On Thursday 24 July 2008 01:47, Chris Lattner wrote: > On Jul 23, 2008, at 8:47 PM, kapil anand wrote: > > Specifically, I need a way to represent indirect branch instruction > > (in binary) as an equivalent LLVM instruction. With switch > > instruction , I would have to list all the possible targets and then > > initialize the corresponding instruction. I was just

Actually, I am trying to implement a frontend for conversion from binary to LLVM. In binary, we would encounter branch indirect instructions like, Br Reg, where Reg would be an equivalent virtual register in LLVM. So, we can't directly implement Switch block method here to represent this instruction as we don't know how the values of Reg are mapped to basic blocks. I was going through

So, that means that &&(Label) operator, which is defined in C++, is also not supported currently in LLVM. I thought I could obtain address of basic block indirectly through this small hack but it does not seem to work. Actually, I tried to make folloing dummy C++ code which uses this operator: *int main(int argc,char** argv) { int x; int y; L1:

The Compilation error I am getting: "Error while compiling ARMJITInfo.cpp.. Selected processor does not support fstmfdd sp!,{d0,d1,d2,d3,d4,d5,d6,d7}.... On Thu, Sep 24, 2009 at 8:45 PM, kapil anand <kapilanand2 at gmail.com> wrote: > Hi all, > > I have an ARM virtual machine with ubuntu and want to port LLVM over that. > In release documents, ARM is not in the list of

Hi all, I have an ARM virtual machine with ubuntu and want to port LLVM over that. In release documents, ARM is not in the list of supported platforms. I tried to compile LLVM on ARM platform and ran into an error. Has anyone tried to port LLVM onto ARM before? Is it going to require lots of changes? Thanks --Kapil -------------- next part -------------- An HTML attachment was scrubbed...

Hi Kapil! LLVM both builds and runs fine on ARM Linux. I am running a public buildbot for the llvm project that are compiling and testing llvm on arm-linux daily and this machine are running Ubuntu Jaunty. http://google1.osuosl.org:8011/builders/llvm-arm-linux I have successfully compiled LLVM on ARM using GCC 4.3.3 on a Ubuntu Jaunty system and GCC 4.4 on a Ubuntu Karmic system. Do you use

My god! I would love a branch predictor! It would simplify many aspects of my register allocator. Second, I am surprised it did not make it into the tree. Since more is being done with register allocation as a while "RegAllocBasic" was just put in, I hope this is looked at again. Do you have a working svn copy? Also, could you send me a copy/link to that '94 paper off the list

Hello Kapil, I have implemented a static profiler for LLVM as a google summer of code project in 2009. I wrote it for the 2.4 branch, but the implementation never made into the tree. I have recently ported it to LLVM 2.8, but I haven't tested it. You can take a look at the code from: http://homepages.dcc.ufmg.br/~rimsa/tools/stprof-llvm.patch The implementation is based on Wu's

You said it was expensive, but if you had to put a big-o estimate on it, what would it be? -Thanks Jeff Kunkel On Tue, Nov 2, 2010 at 8:54 PM, Andrei Alvares <logytech at gmail.com> wrote: > Hello Jeff, > > On Tue, Nov 2, 2010 at 9:17 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > > My god! I would love a branch predictor! It would simplify many aspects > of >

Thanks Andrei! I haven't read the paper. I would see whether this fulfills my requirements or whether I need to make any changes. --Kapil On Tue, Nov 2, 2010 at 12:43 PM, Andrei Alvares <logytech at gmail.com> wrote: > Hello Kapil, > > I have implemented a static profiler for LLVM as a google summer of > code project in 2009. I wrote it for the 2.4 branch, but the >

On Jul 23, 2008, at 8:47 PM, kapil anand wrote: > > Specifically, I need a way to represent indirect branch instruction > (in binary) as an equivalent LLVM instruction. With switch > instruction , I would have to list all the possible targets and then > initialize the corresponding instruction. I was just thinking > whether it might be possible to have some kind of

Hi all, Does LLVM infrastructure contain implementation of any static profiling algorithm apart from "Spill-Weight" calculation present in Live Intervals class? The future work page does suggest implementation of some "static profiling" algorithms to make an educated guesses about the relative execution frequencies of various parts of the code. Thanks --Kapil --------------

Hello Jeff, On Tue, Nov 2, 2010 at 9:17 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > My god! I would love a branch predictor! It would simplify many aspects of > my register allocator. The branch predictor of the implementation is not as accurate as the one from the paper, but it is close enough. Unfortunately, the branch predictor is a very expensive pass, because it relies on

Hi, I have been working on implementing new analysis for a LLVM module. For that, I need that Call Graph of the module. Inside the CallGraph file, the constructor has been declared "protected" hence I can't define its instance and thus use the CallGraph for further analysis. So, what are the ways of building and using Call Graph of a module. Do I need to make my new analysis as

Hi Jeff, There is an algorithm to build the dominator tree that is O(n2), where n is the number of nodes on the control flow graph. I believe exists another that is linear, but I don't which one of them is implemented in LLVM. The problem is that the branch predictor requires post dominance information. None of the LLVM basic passes require post dominance information (AFAIK), hence it is

On Tue, Nov 2, 2010 at 12:28 AM, kapil anand <kapilanand2 at gmail.com> wrote: > Hi all, > > Does LLVM infrastructure contain implementation of any static profiling > algorithm apart from "Spill-Weight" calculation present in Live Intervals > class? The future work page does suggest implementation of some "static > profiling" algorithms to make an