similar to: [LLVMdev] What happened to XCHG_rr?

On Jul 20, 2008, at 11:50 AM, Fernando Magno Quintao Pereira wrote: > I am updating from LLVM 2.1 to current trunk. The names that I was > using > in LLVM 2.1 were: XCHG8rr, XCHG16rr, XCHG32rr and XCHG64rr. > > Ps.: Evan, thank you for answering the question about IMPLICIT_DEF's. I think they were removed just because noone was using them. Also, the JIT encoding may have

I was using them to do SSA-elimination after register allocation. I can implement swaps using three XOR's, but then the code becomes a little bigger and slower. I think even for the sake of completeness, the X86 back-end should offer the possibility of swapping two registers with one single instruction. Do you guys think there is any possibility that those instructions could come back to

Dear guys, what is the best way to implement a swap of floating point registers in X86? For the integer registers, I am using xchg. Is there a similar instruction for floating point? My function to insert swaps is like: void X86RegisterInfo::swapRegs( MachineBasicBlock & mbb, MachineBasicBlock::iterator mi, unsigned r1, unsigned r2, const TargetRegisterClass

Guys, I think I figure out the way that the current LLVM allocators are handling IMPLICIT_DEF's. One question more: why are you adding null length intervals to IMPLICIT_DEF instructions? If they were non-null, I think the code to handle them would be more homogeneous, e.g a traversal of the intervals during register allocation would already reveal virtuals defined implicitly. best,

Hi, guys. sorry if this has already been discussed, but I still feel like clarifying: how should the register allocator handle IMPLICIT_DEF instructions? The LiveIntervalAnalysis class is assigning them zero length intervals. After I removed this, e.g, by removing the lines: if (mi->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) { DOUT << "is a implicit_def\n";