similar to: [LLVMdev] VFCmp failing when unordered or UnsafeFPMath on x86

On Jun 13, 2008, at 12:27 AM, Nicolas Capens wrote: > Hi all, > > When trying to generate a VFCmp instruction when UnsafeFPMath is set > to true I get an assert “Unexpected CondCode” on my x86 system. This > also happens with UnsafeFPMath set to false and using an unordered > compare. Could someone look into this? > > While I’m at it, is there any reason why only the

On Jun 13, 2008, at 12:27 AM, Nicolas Capens wrote: > Hi all, > > When trying to generate a VFCmp instruction when UnsafeFPMath is set > to true I get an assert “Unexpected CondCode” on my x86 system. This > also happens with UnsafeFPMath set to false and using an unordered > compare. Could someone look into this? Please provide a testcase. > > While I’m at it, is

Hi Chris, I've attached a replacement of fibonacci.cpp that reproduces the issue on x86/SSE systems. Regarding the definition of the VFCmp instruction, I think it would really be a lot more valuable to define it as returning all 1's or all 0's per element. Just setting the most significant bit is pretty much worthless (someone correct me if I'm wrong). I checked and I

On Jun 13, 2008, at 12:27 AM, Nicolas Capens wrote: > Hi all, > > When trying to generate a VFCmp instruction when UnsafeFPMath is set > to true I get an assert “Unexpected CondCode” on my x86 system. This > also happens with UnsafeFPMath set to false and using an unordered > compare. Could someone look into this? Have you filed a bug? > > While I’m at it, is there

Hi Nate! I don't see how that would work. Select doesn't work per element. Say we're trying to vectorize the following C++ code: if(v[0] < 0) v[0] += 1.0f; if(v[1] < 0) v[1] += 1.0f; if(v[2] < 0) v[2] += 1.0f; if(v[3] < 0) v[3] += 1.0f; With SSE assembly this would be as simple as: movaps xmm1, xmm0 // v in xmm0 cmpltps xmm1, zero // zero =

Hi, I have some questions as to the definition of various vector instructions. In particular, I believe there are some gaps and inconsistencies in the vector instructions, and I'm interested in hearing whether you agree that these should be improved or whether there are other ways to solve these problems. === 1. Shufflevector only accepts vectors of the same type Shufflevector seems overly

On Jun 26, 2008, at 1:56 PM, Stefanus Du Toit wrote: > Hi, > > I have some questions as to the definition of various vector > instructions. In particular, I believe there are some gaps and > inconsistencies in the vector instructions, and I'm interested in > hearing whether you agree that these should be improved or whether > there are other ways to solve these problems.

On Jun 24, 2009, at 12:47 AM, Duncan Sands wrote: > Hi Nick, > >> Now that icmp and fcmp have supported returning vectors of i1 for a >> while, > > the code generators don't know how to codegen vectors of i1, so does > this actually work? No, but there are no clients of them yet. -Chris

On Jun 24, 2009, at 10:02 AM, Chris Lattner wrote: > > On Jun 24, 2009, at 12:47 AM, Duncan Sands wrote: > >> Hi Nick, >> >>> Now that icmp and fcmp have supported returning vectors of i1 for a >>> while, >> >> the code generators don't know how to codegen vectors of i1, so does >> this actually work? > > No, but there are no

I'm getting this: /home/ghost/Work/llvm-cvs/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp: In member function `void llvm::SelectionDAGLowering::visitSetCC(llvm::User&, llvm::ISD::CondCode, llvm::ISD::CondCode, llvm::ISD::CondCode)': /home/ghost/Work/llvm-cvs/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1107: error: ` UnsafeFPMath' undeclared (first use this function)

On Thu, Mar 9, 2017 at 9:35 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > On 02/25/2017 03:06 AM, vivek pandya via llvm-dev wrote: > > Note: Question is written after describing what I have coded. > > Hello LLVMDevs, > > I am trying to impliment floating point comparsion for an architecture > which > supports following type of floating point comparision if FPU

On 03/14/2017 07:16 AM, vivek pandya wrote: > Hello Hal, > setCondCodeAction(expand) for un ordered comparison generates > semantically wrong code for me for example SETUNE gets converted to > SETOE that causes infinite loops. Can you please explain what is happening? It sounds like a bug we should fix. > > What is ideal place where I can convert unordered comparison to un

Hi all, I'm trying to generate code containing an ordered float compare for equality, and select. The resulting code however has an unordered compare and some Boolean logic that I think could be eliminated. In C syntax the code looks like this: float x, y; int a, b, c if(x == y) // Rotate the integers { int t; t = a; a = b;

Note: Question is written after describing what I have coded. Hello LLVMDevs, I am trying to impliment floating point comparsion for an architecture which supports following type of floating point comparision if FPU is available: fcmp.un --> true if one of the operand is NaN fcmp.lt --> ordered less than, if any input NaN then return false fcmp.eq --> ordered equal, if any input NaN

To continue the discussion I started last year (see the link below) on embedding command-line options in bitcode, I came up with a plan to improve the way the backend changes UnsafeFPMath on a per-function basis. The code in trunk currently resets TargetOptions::UnsafeFPMath at the beginning of SelectionDAGISel::runOnMachineFunction to enable compiling one function with “unsafe-fp-math=true” and

Both ZF and PF will be set if unordered, so the code below is IEEE correct...you want to generate 'fcmp ueq' instead of 'fcmp oqe' This is the resulting x86 assembly code: movss xmm0,dword ptr [ecx+4] ucomiss xmm0,dword ptr [ecx+8] sete al setnp dl test dl,al mov edx,edi cmovne edx,ecx cmovne ecx,esi cmovne

Hi Dan, Thanks for your comments. I've responded inline below. On 26-Jun-08, at 6:49 PM, Dan Gohman wrote: > On Jun 26, 2008, at 1:56 PM, Stefanus Du Toit wrote: >> >> === >> 1. Shufflevector only accepts vectors of the same type >> >> I would propose to change the syntax from: >> >>> <result> = shufflevector <n x <ty>>

Hi all, I'm trying to implement a floating-point 'min' and 'max' operation using select. For 'min' I get the expected x86 assembly minss instruction, but for 'max' I get a branch instead of maxss. The corresponding C syntax code looks like this: float z = (x > y) ? x : y; Any clues? Could someone maybe explain to me the basics of

Hi, In unordered floating point comparison before making a call for comparison proper one node called UO_F32 is generated. In targets this node is replaced with a call to __unordsf2. My doubts here 1) What are these UO_F32 and O_F32 nodes for? 2) What is this function (__unordsf2) supposed to do? Regards Sachin -------------- next part -------------- An HTML attachment was

Hi All, I noticed LLVM target independent side is converting an ordered less than "setolt" into unordered greater than "setuge" operation. There are no target hooks to control going from the ordered mode into unordered. I am trying to figure out the best way to support unordered operation on Hexagon. We don't have a single instruction to do unordered operation. So we