similar to: [LLVMdev] LLVM project binary size

Displaying 20 results from an estimated 9000 matches similar to: "[LLVMdev] LLVM project binary size"

2008 May 28
0
[LLVMdev] LLVM project binary size
On May 25, 2008, at 11:29 PM, Nicolas Capens wrote: > Hi all, > > I’m a little bit worried about the sheer size of the resulting > binaries of a project using LLVM. The medium large project for which > I’m planning to use it (which currently uses a custom dynamic code > generator), produces a compact 1.6 MB binary. When I compile LLVM’s > simple ‘Fibonacci’ example
2008 Jul 14
5
[LLVMdev] Spilled variables using unaligned moves
Hi all, It looks like vector spills don't use aligned moves even though the stack is aligned. This seems like an optimization opportunity. The attached replacement of fibonacci.cpp generates x86 code like this: 03A70010 push ebp 03A70011 mov ebp,esp 03A70013 and esp,0FFFFFFF0h 03A70019 sub esp,1A0h ... 03A7006C movups xmmword ptr
2008 Jul 14
0
[LLVMdev] Spilled variables using unaligned moves
This is on Windows / Cygwin? I think the dynamic stack pointer re- alignment doesn't happen until post- register allocation. Assuming there aren't other instructions between the prologue and the first movups that mess up esp (there shouldn't), this is indeed a bug. Please file a bug and attach a bc file. Thanks. Evan On Jul 14, 2008, at 7:43 AM, Nicolas Capens wrote: > Hi
2008 Jul 12
2
[LLVMdev] Shuffle regression
Hi all, I think I found a regression in the shuffle instruction. I've attached a replacement of fibonacci.cpp to reproduce the issue. It runs fine on release 2.3 but revision 52648 fails, and I suspect that the issue is still present. 2.3 generates the following x86 code: 03A10010 push ebp 03A10011 mov ebp,esp 03A10013 and esp,0FFFFFFF0h 03A10019
2008 May 26
0
[LLVMdev] LLVM project binary size
Hi Nicholas, On May 26, 2008, at 02:29, Nicolas Capens wrote: > I realize LLVM is a complex and feature rich project but could > anyone give me a rough idea of where most of the executable size is > coming from, and maybe give some ideas on how to reduce it if > possible? 'nm' can give you this information on Unix. I don't know what the equivalent in the VS
2008 Jul 31
5
[LLVMdev] Generating movq2dq using IRBuilder
On Jul 31, 2008, at 7:22 AM, Nicolas Capens wrote: > In the same breath I’d also like to kindly ask if someone could have > a look at the reverse operations, namely trunk from 128 to 64 bit > using movdq2q, and 128 to 32 and 64 to 32 using movd. This also > seems related to Bug 2585. Thanks again. The operations you're describing can be represented as insertelement and
2008 Jul 31
2
[LLVMdev] Generating movq2dq using IRBuilder
Hi all, How do I generate the movq2dq SSE2 instruction using the IRBuilder? There is no zext from 64-bit to 128-bit (corresponding to MMX to XMM register transfer) as far as I can tell. So I've tried inserting an i64 into a v2i64, which generates valid code but rather a number of stores and loads on the stack instead of a single movq2dq. Looking though the code, I found a pattern for
2008 Jul 15
1
[LLVMdev] Spilled variables using unaligned moves
Hi Evan, Could you maybe point me to the source files where this issue might originate? I'd like to learn more about LLVM's innards but so far I've just scraped the surface and I don't know where what phase of instruction selection / register allocation / stack layout / etc. happens. If I understand correctly this issue might be fixed by moving stack pointer alignment
2008 Jul 14
0
[LLVMdev] Spilled variables using unaligned moves
On Jul 14, 2008, at 7:43 AM, Nicolas Capens wrote: > Hi all, > > It looks like vector spills don’t use aligned moves even though the > stack is aligned. This seems like an optimization opportunity. What target is this? Linux doesn't have a 16-byte aligned stack. -Chris > > The attached replacement of fibonacci.cpp generates x86 code like > this: > > 03A70010
2008 Jul 10
3
[LLVMdev] InstructionCombining forgets alignment of globals
Hi all, The InstructionCombining pass causes alignment of globals to be ignored. I've attached a replacement of Fibonacci.cpp which reproduces this (I used 2.3 release). Here's the x86 code it produces: 03C20019 movaps xmm0,xmmword ptr ds:[164E799h] 03C20020 mulps xmm0,xmmword ptr ds:[164E79Ah] 03C20027 movaps xmmword ptr ds:[164E799h],xmm0 03C2002E
2008 May 20
2
[LLVMdev] Making use of SSE intrinsics
Hi all, I'd like to make use of some specific x86 Streaming SIMD Extension instructions, but I don't know where to start. For instance the 'rcpps' instructions computes a low precision but fast reciprocal. I've noticed that LLVM supports intrinsics, but I couldn't find any information on how to use them. I've tried digging through the LLVM-GCC code but it's just
2008 Jun 13
6
[LLVMdev] VFCmp failing when unordered or UnsafeFPMath on x86
Hi all, When trying to generate a VFCmp instruction when UnsafeFPMath is set to true I get an assert "Unexpected CondCode" on my x86 system. This also happens with UnsafeFPMath set to false and using an unordered compare. Could someone look into this? While I'm at it, is there any reason why only the most significant bit of the return value of VFCmp is defined (according to
2008 Jul 12
0
[LLVMdev] Shuffle regression
I have fixed a related bug: 52740. Can you check if that fixes this problem? Evan On Jul 11, 2008, at 6:43 PM, Nicolas Capens wrote: > Hi all, > > I think I found a regression in the shuffle instruction. I’ve > attached a replacement of fibonacci.cpp to reproduce the issue. It > runs fine on release 2.3 but revision 52648 fails, and I suspect > that the issue is still
2008 Jun 16
1
[LLVMdev] VFCmp failing when unordered or UnsafeFPMath on x86
Hi Chris, I've attached a replacement of fibonacci.cpp that reproduces the issue on x86/SSE systems. Regarding the definition of the VFCmp instruction, I think it would really be a lot more valuable to define it as returning all 1's or all 0's per element. Just setting the most significant bit is pretty much worthless (someone correct me if I'm wrong). I checked and I
2008 Aug 01
0
[LLVMdev] Generating movq2dq using IRBuilder
Hi Dan, Yes, they could be represented with insertelement and extractelement, but I don't think they actually generate optimal code using movq2dq and such. Else both bugs 2584 and 2585 would be fixed. Anyway, I'm actually already encouraged to get involved myself. I'm quite experienced with MMX and SSE but I'm still trying to learn more about how LLVM does instruction selection
2008 May 27
3
[LLVMdev] Float compare-for-equality and select optimization opportunity
Hi all, I'm trying to generate code containing an ordered float compare for equality, and select. The resulting code however has an unordered compare and some Boolean logic that I think could be eliminated. In C syntax the code looks like this: float x, y; int a, b, c if(x == y) // Rotate the integers { int t; t = a; a = b;
2008 Jul 31
0
[LLVMdev] Generating movq2dq using IRBuilder
On 31-Jul-08, at 2:38 PM, Dan Gohman wrote: > On Jul 31, 2008, at 7:22 AM, Nicolas Capens wrote: >> In the same breath I’d also like to kindly ask if someone could have >> a look at the reverse operations, namely trunk from 128 to 64 bit >> using movdq2q, and 128 to 32 and 64 to 32 using movd. This also >> seems related to Bug 2585. Thanks again. > > The operations
2008 May 20
0
[LLVMdev] Making use of SSE intrinsics
On Tue, May 20, 2008 at 5:03 AM, Nicolas Capens <nicolas at capens.net> wrote: > LoadInst *x = new LoadInst(ptr_x, "", false, basicBlock); > > // y = rcpps(x) // FIXME > StoreInst *storeResult = new StoreInst(y, ptr_y, false, basicBlock); Using an IRBuilder, something like the following (uncompiled, but it's at least approximately right): Value* x =
2008 Jul 31
0
[LLVMdev] Generating movq2dq using IRBuilder
In the same breath I'd also like to kindly ask if someone could have a look at the reverse operations, namely trunk from 128 to 64 bit using movdq2q, and 128 to 32 and 64 to 32 using movd. This also seems related to Bug 2585. Thanks again. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Nicolas Capens Sent: Thursday, 31 July, 2008 16:03 To:
2008 Aug 01
1
[LLVMdev] Generating movq2dq using IRBuilder
Hi Stefanus, I'm not if using MMX instructions when doing operations on 64-bit vectors is so terrible? With x86-64 you have double the registers, but it comes at the cost of longer instruction encodings. So there's probably no benefit using SSE. Or am I missing something? Cheers, Nicolas -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at