similar to: [LLVMdev] LLVM instruction scheduler

Hi, I'm making a plot in which the title takes up two lines. The title contains a subscript but when I look at the plot it does'nt seem tocome out properly. The code I'm using is: xtxt = expression(paste('Observed -log( ', IC[50], ' )')) ytxt = expression(paste('Predicted -log( ', IC[50], ' )')) mtxt = expression(paste('Plot of Observed

Hi, I have a package for which I'm writing a vignette. The vignette looks fine as indicated by R CMD check. However after installing the package (in my personal R library location) doing vignette('rcdk') says Warning message: vignette 'rcdk' *not* found But I can see the PDF file located under rcdk/doc in the R library directory. The header of the Rnw file is %

On Sep 17, 2013, at 11:04 AM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > 1. The SD schedulers significantly impact the spill counts and the execution times for many benchmarks, but the machine instruction (MI) scheduler in 3.3 has very limited impact on both spill counts and execution times. Is this because most of you work on MI did not make it into the 3.3 release?

Sent from my iPhone On Jun 28, 2013, at 2:38 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Hi, > > We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been

Hi, I'm interested in the two pre-RA instruction schedulers used in LLVM, list-hybrid and list-ilp. I've done some digging on the internet and played around with executing some test files using the two schedules. However, I'm still uncertain of the behaviors and heuristics used in each. For example, the XXXX_ls_rr_sort::isReady for hybrid includes a 3 cycle readydelay (seems

Thank you for the answers! We are currently trying to test the MI scheduler. We are using LLVM 3.3 with Dragon Egg 3.3 on an x86-64 machine. So far, we have run one SPEC CPU2006 test with the MI scheduler enabled using the option -fplugin-arg-dragonegg-llvm-option='-enable-misched:true' with -O3. This enables the machine scheduler in addition to the SD scheduler. We have verified this by

Hi, I would like to get some feedback about the current status of the pre-RA machine scheduler bidirectional scheduling. I have tried enabling this on SystemZ, and found that it slightly increases spilling generally (in one benchmark with as much as 5%). Benchmarking do not indicate that bidirectional would be a win, either. Is this within the expected, or does it indicate something in the

On May 10, 2012, at 9:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: >> - Target pass configuration: DONE >> - MachineScheduler pass framework: DONE >> - MI Scheduling DAG: DONE >> - AliasAnalysis aware DAG option: In review (Sergei) >> - Bidirectional list scheduling: DONE >> - LiveInterval Update: WIP (simple instruction reordering is >> supported)

On May 8, 2012, at 3:02 PM, dag at cray.com wrote: > Hi everyone, > > As I've mentioned before we are doing some work on the LLVM scheduler to > improve it. Specifically, we are working to get loads and stores to > move past each other when possible. > > When I asked about enhancing scheduler heuristics a month or so ago, I > got a response about a MachineInstr

I see that there are several options to influence instruction scheduling, but there doesn't seem to be a lot of information about what they do, for example: -misched-topdown -misched-bottomup The description in MachineScheduler.cpp says: "Force top-down list scheduling" and "Force bottom-up list scheduling" Which isn't too helpful - where might I want to use these?

Hi everyone, As I've mentioned before we are doing some work on the LLVM scheduler to improve it. Specifically, we are working to get loads and stores to move past each other when possible. When I asked about enhancing scheduler heuristics a month or so ago, I got a response about a MachineInstr scheduler and that that was the way of the LLVM future. Is that so? Is the ScheduleDAG going

In my last message, I explained the goals of the generic MI scheduler and current status. This week, I'll see if we can enable MI scheduling by default for x86. I'm not sure which flags you're using to test it now. But by making it default and enabling the corresponding coalescer changes, we can be confident that benchmarking efforts are improving on the same baseline. At that point, I

#I wish to create a "list of three dataframes" ("results2") from a "list of two dataframes" (temp) and a dataframe ("c")? #Please advise. a <- data.frame(x=c(1,2,3),y=c(5,7,9)) b <- data.frame(x=c(2,4,7,9),y=c(2,3,5,4)) c <- data.frame(x=c(22,34,7,9),y=c(52,63,5,4)) results1 <- list(a,b,c) #what I want #but this is how I need to get there

On Thu, 10 May 2012 20:33:53 -0700 Andrew Trick <atrick at apple.com> wrote: > On May 9, 2012, at 8:34 AM, dag at cray.com wrote: > > > Andrew Trick <atrick at apple.com> writes: > > > >>> When I asked about enhancing scheduler heuristics a month or so > >>> ago, I got a response about a MachineInstr scheduler and that > >>> that

On May 9, 2012, at 8:34 AM, dag at cray.com wrote: > Andrew Trick <atrick at apple.com> writes: > >>> When I asked about enhancing scheduler heuristics a month or so ago, I >>> got a response about a MachineInstr scheduler and that that was the way >>> of the LLVM future. Is that so? Is the ScheduleDAG going away? >> >> You sent a lengthy RFC

Hi, We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been implemented to replace (or work with?) the selection DAG (SD) scheduler. However, I could not find any document that

On Jul 2, 2013, at 2:35 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Thank you for the answers! We are currently trying to test the MI scheduler. We are using LLVM 3.3 with Dragon Egg 3.3 on an x86-64 machine. So far, we have run one SPEC CPU2006 test with the MI scheduler enabled using the option -fplugin-arg-dragonegg-llvm-option='-enable-misched:true' with -O3.

On Apr 20, 2012, at 10:31 AM, dag at cray.com wrote: > I'd like to begin a project to rework the scheduler to address some > problems we've discovered on this end. The goal is to get a more > configurable/flexible scheduler while simplifying maintenance by > separating policy from implementation to get independent and > interchangeable parts. > > This is going to be

I think those should be considered internal options for (llvm codegen) developers, a normal compiler user should not need to use any of them. Of course you can look around the llvm sourcecode (esp. in lib/CodeGen/MachineScheduler.cpp) and see what cl::opt options are available and how they affect the scheduler operation. In case of the MachineScheduler all settings are the same regardless of the

Hi, Thanks for your explanations! How is the big picture for supporting in-order VLIW architectures and the like though? I am asking because I am currently implementing instruction scheduling in our own backend for our custom Patmos processor, for which I need to support both branch delay slots and bundles, some restrictions regarding bundles. For the moment, I am quite happy with a simple