Displaying 20 results from an estimated 3000 matches similar to: "[LLVMdev] Reference Manual Clarifications"
2018 Sep 25
2
Unsafe floating point operation (FDiv & FRem) in LoopVectorizer
Hi,
Consider the following test case:
int foo(float *A, float *B, float *C, int len, int VSMALL) {
for (int i = 0; i < len; i++)
if (C[i] > VSMALL)
A[i] = B[i] / C[i];
}
In this test the div operation is conditional but llvm is generating unconditional div for this case:
vector.body: ; preds = %vector.body, %vector.ph
%index = phi i64 [
2006 Apr 18
1
[patch] sparc build fix
add object rules so that the division, remainder and friends get
really build on sparc, patch from Fabio M. Di Nitto <fabbione@ubuntu.com>.
reworked to apply on latest git tree.
Signed-off-by: maximilian attems <maks@sternwelten.at>
---
Has been since long in the Debian and Ubuntu klibc.
diff --git a/klibc/arch/sparc/Makefile.inc b/klibc/arch/sparc/Makefile.inc
index
2008 Mar 31
7
[LLVMdev] Reference Manual Clarifications
Here is a patch containing all but one of the changes. I realized that
the remainder/modulo discussion does indeed belongs to the srem
instruction. The semantics of urem are obvious and need no further
clarification.
Best Regards,
Jon
1572,1573c1572,1575
< notation (see below). Floating point constants must have a <a
< href="#t_floating">floating point</a>
2008 Mar 31
0
[LLVMdev] Reference Manual Clarifications
Hi Jon,
Please you'll want to submit patches as unified diffs and as
attachments.
I notice you're using Thunderbird, so I refer you to this tip:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2008-January/011992.html
Although this note doesn't apply to how you included your original
patch (looks like you pasted it in), Thunderbird has default
attachment handling settings which
2015 Oct 05
3
RFC: Pass for lowering "non-linear" arithmetics of illegal types
Hi LLVM,
This is my idea I had some time ago, when I realized that LLVM did not
support legalization of some arithmetic instructions like mul i256. I have
implemented very simple and limited version of that in my project. Is it
something LLVM users would appreciate?
1. The pass transforms IR and is meant to be run before CodeGen (after
IR optimizations).
2. The pass replaces
2020 Feb 07
2
Why does FPBinOp(X, undef) -> NaN?
On Fri, Feb 7, 2020 at 12:29 PM Nuno Lopes <nunoplopes at sapo.pt> wrote:
>
> It's not correct (output of Alive2):
>
> define half @fn(half %a) {
> %b = fadd half %a, undef
> ret half %b
> }
> =>
> define half @fn(half %a) {
> ret half undef
> }
> Transformation doesn't verify!
> ERROR: Value mismatch
>
> Example:
> half %a
2008 Aug 19
2
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
Hi all,
I'm trying to implement llvm.memory.barrier on PowerPC. I've modelled
my patch (attached) on the implementation in X86, but when I try and
compile my test file (also attached) with llc I get the error "Cannot
yet select: 0x10fa4ad0: ch = MemBarrier 0x10fa4828, 0x10fa4c68,
0x10fa4be0, 0x10fa4be0, 0x10fa4be0, 0x10fa4be0". This presumably
means my "membarrier"
2008 Aug 22
3
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
No, I don't.
Cheers,
Gary
Dale Johannesen wrote:
> This looks OK to check in, do you have write access?
>
> On Aug 21, 2008, at 6:38 AMPDT, Gary Benson wrote:
>
> >Dale Johannesen wrote:
> >>On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote:
> >>>I'm trying to implement llvm.memory.barrier on PowerPC. I've
> >>>modelled my patch
2020 Feb 07
3
Why does FPBinOp(X, undef) -> NaN?
I came across this comment in SelectionDAG.cpp:
case ISD::FADD:
case ISD::FSUB:
case ISD::FMUL:
case ISD::FDIV:
case ISD::FREM:
// If both operands are undef, the result is undef. If 1 operand is undef,
// the result is NaN. This should match the behavior of the IR optimizer.
That isn't intuitive to me. I would have expected a binary FP
operation with one undef operand to
2008 Aug 21
2
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
Dale Johannesen wrote:
> On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote:
> > I'm trying to implement llvm.memory.barrier on PowerPC. I've
> > modelled my patch (attached) on the implementation in X86, but
> > when I try and compile my test file (also attached) with llc I
> > get the error "Cannot yet select: 0x10fa4ad0: ch = MemBarrier
> >
2010 Mar 12
0
[LLVMdev] Smaller than 32-bit?
Hi Russell-
The PIC16 is an 8-bit target, and the msp430 is a 16-bit target. The rules about the largest supported integer no longer apply as much- for most operations, codegen can now handle arbitrary precision (exceptions: mul, udiv, urem, sdiv, srem). For those five, library calls should be emitted for big integers - best way to check if they're supported is to just try them :)
Alastair
2014 Apr 24
4
[LLVMdev] Proposal: add intrinsics for safe division
Hi,
I’d like to propose to extend LLVM IR intrinsics set, adding new ones for safe-division. There are intrinsics for detecting overflow errors, like sadd.with.overflow, and the intrinsics I’m proposing will augment this set.
The new intrinsics will return a structure with two elements according to the following rules:
safe.[us]div(x,0) = safe.[us]rem(x,0) = {0, 1}
safe.sdiv(min<T>, -1) =
2017 Jul 31
4
unsigned operations with negative numbers
Hello,
I want to know, if I can always assume that when I do unsigned operations
like
udiv, urem
I will get the both operands converted to unsigned values? with under
optimized version of code I sometimes receive these lines:
unsigned a = 123;
int b = -2;
int c = a / b;
-> %1 = udiv i32 123, -2
and get the result 0. Will it always be zero? or is it undefined?
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
Per subject, this patch adding an additional pass to handle vector
operations; the idea is that this allows removing the code from
LegalizeDAG that handles illegal types, which should be a significant
simplification. There are still some issues with this patch, but does
the approach look sane?
-Eli
-------------- next part --------------
Index: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
2012 Apr 25
0
[LLVMdev] [PATCH][RFC] NVPTX Backend
On 4/24/2012 1:50 PM, Justin Holewinski wrote:
>
> Hi LLVMers,
>
> We at NVIDIA would like to contribute back to the LLVM open-source
> community by up-streaming the NVPTX back-end for LLVM. This back-end
> is based on the sources used by NVIDIA, and currently provides
> significantly more functionality than the current PTX back-end. Some
> functionality is currently
2014 Apr 25
4
[LLVMdev] Proposal: add intrinsics for safe division
On April 25, 2014 at 9:52:35 AM, Eric Christopher (echristo at gmail.com) wrote:
Hi Michael,
> I’d like to propose to extend LLVM IR intrinsics set, adding new ones for
> safe-division. There are intrinsics for detecting overflow errors, like
> sadd.with.overflow, and the intrinsics I’m proposing will augment this set.
>
> The new intrinsics will return a structure with two
2010 Mar 11
2
[LLVMdev] Smaller than 32-bit?
Does LLVM support any target platforms on which the natural integer
size/pointer size is smaller than 32 bits? For example, I noticed
mention of PIC16, is that such a platform?
If so, does the usual rule about the largest supported integer being
the size of two pointers still apply? So that on that platform you
can't use 64-bit integers, but you can use 32-bit integers?
2006 Nov 16
0
[LLVMdev] LLVM 1.9 Release Announcement [draft #1]
Hi All,
Here's the first draft of the release announcement for LLVM 1.9 that
I'm working on. I'm sure I've forgotten and overlooked something, if
so,
please let me know!
----- 8< ------ 8< -----
<notes>
Note: LLVM now correctly builds itself and passes all regression
tests on
Darwin X86 and Darwin PPC. No one has tried other targets to my
knowledge.
We hit
2008 Aug 22
0
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
OK, I've checked it in for you, thanks. Please do contact Chris
about write access.
On Aug 22, 2008, at 12:38 AMPDT, Gary Benson wrote:
> No, I don't.
>
> Cheers,
> Gary
>
> Dale Johannesen wrote:
>> This looks OK to check in, do you have write access?
>>
>> On Aug 21, 2008, at 6:38 AMPDT, Gary Benson wrote:
>>
>>> Dale Johannesen
2008 Aug 21
0
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote:
> Hi all,
>
> I'm trying to implement llvm.memory.barrier on PowerPC. I've modelled
> my patch (attached) on the implementation in X86, but when I try and
> compile my test file (also attached) with llc I get the error "Cannot
> yet select: 0x10fa4ad0: ch = MemBarrier 0x10fa4828, 0x10fa4c68,
> 0x10fa4be0,