similar to: [LLVMdev] reg_iterator Caveats

On Mar 30, 2008, at 11:17 AM, David Greene wrote: > I'm forwarding this to llvmdev so it doesn't get lost in the sea of > commits... reg_iterators are independent of SSA or not. The basic issue is that if you loop over uses or defs of a register, it will return *all* the uses/defs of that register in the current function. If the value is SSA form, it is reasonable to say

On Sunday 30 March 2008 01:30:40 pm Chris Lattner wrote: > On Mar 30, 2008, at 11:17 AM, David Greene wrote: > > I'm forwarding this to llvmdev so it doesn't get lost in the sea of > > commits... > > reg_iterators are independent of SSA or not. The basic issue is that > if you loop over uses or defs of a register, it will return *all* the > uses/defs of that

On Monday 31 March 2008 00:57, Chris Lattner wrote: > On Mar 30, 2008, at 10:42 PM, David A. Greene wrote: > >> SSA form, it is reasonable to say "give me the first def" and expect > >> it to be the only def. For multiply defined values like physregs, > >> this is not true, because the reg can have multiple defs. > > > > Gotcha. This is exactly

On Mon, 31 Mar 2008, Evan Cheng wrote: >> I just discovered that def_itterator (and presumably, reg_iterator) >> doesn't >> include implicit defs, for example at function calls for caller-save >> physical >> registers. Guh. I'm not sure if it should or not, but it's certainly >> necessary information in some cases. Is this expected behavior, or an

On Monday 31 March 2008 18:55, Chris Lattner wrote: > On Mon, 31 Mar 2008, Evan Cheng wrote: > >> I just discovered that def_itterator (and presumably, reg_iterator) > >> doesn't > >> include implicit defs, for example at function calls for caller-save > >> physical > >> registers. Guh. I'm not sure if it should or not, but it's

On Mar 31, 2008, at 2:53 PM, David Greene wrote: > On Monday 31 March 2008 00:57, Chris Lattner wrote: >> On Mar 30, 2008, at 10:42 PM, David A. Greene wrote: >>>> SSA form, it is reasonable to say "give me the first def" and >>>> expect >>>> it to be the only def. For multiply defined values like physregs, >>>> this is not

On Mar 30, 2008, at 10:42 PM, David A. Greene wrote: >> SSA form, it is reasonable to say "give me the first def" and expect >> it to be the only def. For multiply defined values like physregs, >> this is not true, because the reg can have multiple defs. > > Gotcha. This is exactly what I want. Thanks for the explanation. > > For non-SSA values, is there

On Mar 31, 2008, at 4:55 PM, Chris Lattner wrote: > On Mon, 31 Mar 2008, Evan Cheng wrote: >>> I just discovered that def_itterator (and presumably, reg_iterator) >>> doesn't >>> include implicit defs, for example at function calls for caller-save >>> physical >>> registers. Guh. I'm not sure if it should or not, but it's

<div class="socmaildefaultfont" dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" >Matthias,</div> <div dir="ltr" > </div> <div dir="ltr" >Thanks for the response.</div> <div

<div class="socmaildefaultfont" dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div class="socmaildefaultfont" dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" > </div> <div dir="ltr" >Hi all,</div> <div dir="ltr" > </div> <div

On Tue, 1 Apr 2008, David Greene wrote: > On Tuesday 01 April 2008 10:47, David Greene wrote: >>> reg iterators will return everything that is in the function. If the >>> implicit operands haven't been added to the machieninstrs yet, then they >>> won't be returned. >> >> Hmm...this is definitely NOT true in my copy. During register allocation

On Tuesday 01 April 2008 10:47, David Greene wrote: > > reg iterators will return everything that is in the function. If the > > implicit operands haven't been added to the machieninstrs yet, then they > > won't be returned. > > Hmm...this is definitely NOT true in my copy. During register allocation > these implicit defs are not returned. By then the

Hi folks, I would like to find out the machine instructions that use some given registers in the reverse order, and I came across these iterators (use_iterator/reg_iterator). However, there are two things I noticed: 1) These iterators seem to traverse the machine function a bit differently from what I get from the machine function dump. In other words, the use_iterator list is not constructed in

Thanks Quentin. I'm trying to examine from the operands of the return instruction, and then to get the last assignment of those. I thought use_iterator/reg_iterator may suit better than just loop through the machine basicblock in the reverse order. Cheng-Chih On Thu, Sep 25, 2014 at 1:51 PM, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Cheng-Chih, > > On Sep 25,

Dear LLVM guys, I am coding a liveness analysis algorithm, and I found this comment on LiveVariables.cpp: Line 00195 - http://llvm.org/doxygen/LiveVariables_8cpp-source.html : // PhysRegInfo - Keep track of which instruction was the last use of a // physical register. This is a purely local property, because all physical // register references as presumed dead across basic blocks.

On Jan 11, 2008, at 2:00 PM, David Greene wrote: > Is there any way to discover whether a particular operand of a > MachineInst > participates in addressing? That is, if the MachineInst references > memory, > can I tell, given an operand, whether that operand is part of the > address > calculation for the instruction? Nope, not that I know of. > Also, is there any

Is there any way to discover whether a particular operand of a MachineInst participates in addressing? That is, if the MachineInst references memory, can I tell, given an operand, whether that operand is part of the address calculation for the instruction? Also, is there any reasonable way to get the set of machine instructions to which the output(s) of some machine instruction flows? The

On Thu, May 26, 2011 at 15:07:24 +0200, Jonas Paulsson wrote: > In order to get a pre-RA scheduling, I would need something like: > - LiveVars > - PhiElim > - TwoAddr > - LiveIntervals > - Coalescing > - Scheduler (new) > - SlotIndexing > - LiveIntervals2 (new) > - RegAlloc > My qeustion then is, is it really so difficult to create the live intervals

Hi, thank you for your explanations. In order to get a pre-RA scheduling, I would need something like: - LiveVars - PhiElim - TwoAddr - LiveIntervals - Coalescing - Scheduler (new) - SlotIndexing - LiveIntervals2 (new) - RegAllocMy qeustion then is, is it really so difficult to create the live intervals information, with modifications to the original algorithm, or even from scratch?

So if I create a value with a DAG.getUndef(myVT); call during instruction legalization, how can I access that value as input in another BB/DAG (also during instruction legalization) without worrying about live-ins and/or phi nodes? Can I create a single virtual register and build both a CopyToReg and a CopyFromReg node with it? I assumed that would break SSA. Perhaps I should have said that what