similar to: [LLVMdev] What is "strong phi elimination"

Ask an ye shall receive. From the .cpp file: // = = =---------------------------------------------------------------------- ===// // // This pass eliminates machine instruction PHI nodes by inserting copy // instructions, using an intelligent copy-folding technique based on // dominator information. This is technique is derived from: // // Budimlic, et al. Fast copy coalescing and

Do you mean that "normal" SSA phi elimination algorithm is DemotePHI()? Thx, Seung ---- Original message ---- >Date: Mon, 24 Mar 2008 21:43:06 -0700 >From: Chris Lattner <sabre at nondot.org> >Subject: Re: [LLVMdev] What is "strong phi elimination" >To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Cc: Christopher Lamb

On Thu, 12 Apr 2007, Fernando Magno Quintao Pereira wrote: >> I'm definitely interested in improving coalescing and it sounds like >> this would fall under that work. Do you have references to papers >> that talk about the various algorithms? > > Some suggestions: > > @InProceedings{Budimlic02, > AUTHOR = {Zoran Budimlic and Keith D. Cooper and Timothy

Chris Lattner wrote: > On Thu, 12 Apr 2007, Fernando Magno Quintao Pereira wrote: >>> I'm definitely interested in improving coalescing and it sounds like >>> this would fall under that work. Do you have references to papers >>> that talk about the various algorithms? >> Some suggestions: >> >> @InProceedings{Budimlic02, >> AUTHOR =

Chris Lattner wrote: > On Thu, 12 Apr 2007, David Greene wrote: >> As I work toward improving LLVM register allocation, I've >> come across the need to do some refactoring. > > cool. :) One request: Evan is currently out on vacation until Monday. > This is an area that he is very interested in and will want to chime in > on. Please don't start anything

Hi RamShankar, On top of Rafael mentioned ,Please check with lib/CodeGen/StrongPHIElimination.cpp and the papers like Budimlic, et al. Fast copy coalescing and live-range identification. // In Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language // Design and Implementation (Berlin, Germany, June 17 - 19, 2002). // PLDI '02. ACM, New York, NY, 25-32. Boissinot,

Hi, I am a newbie to llvm. I am wondering what approach is used when coming out of SSA form. I also appreciate pointers on where to look in the source code for this phase. Best regards, Ram Ramshankar -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120824/87feb1d3/attachment.html>

On 24 August 2012 02:27, Ramanarayanan, Ramshankar <Ramshankar.Ramanarayanan at amd.com> wrote: > Hi, > > > > I am a newbie to llvm. I am wondering what approach is used when coming out > of SSA form. I also appreciate pointers on where to look in the source code > for this phase. > lib/CodeGen/PHIElimination.cpp is probably what you want. > > Best regards,

I was wondering, is there any way to express in the IR that an instruction/instruction sequence/basic block/region/function/module/whatever is an alternate version of another? e.g. let's keep things simple and say that I have an instruction I. An optimization pass reads it and could be able to produce one or more functionally-equivalent instructions I1, ..., In without being really able

Hello, I am implementing a code transformation that would heavily benefit from the CodeGen/StrongPHIElimination pass, but on the two bytecode files I've tested it on so far llc segfaults on both. I see there have been no substantive changes to this code since the middle of last year. Could someone please tell me what the status of this pass is? Thank you. Marc -------------- next part

On Jun 8, 2012, at 9:02 AM, Hal Finkel <hfinkel at anl.gov> wrote: > On Fri, 8 Jun 2012 08:49:32 -0700 > Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: >> When machine code is still in SSA form, there are restrictions on >> what can be done with physical registers, which by their nature can't >> be in SSA form. Lang and I have been trying to come up

On Fri, 08 Jun 2012 09:24:16 -0700 Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Jun 8, 2012, at 9:02 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > > On Fri, 8 Jun 2012 08:49:32 -0700 > > Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > >> When machine code is still in SSA form, there are restrictions on > >> what can

I'm the person who wrote it, and it's not really maintained, as we decided we wanted to go in a different direction long-term by having fewer passes making independent coalescing decisions rather than more. At the time I stopped working on it, it worked fine on x86 but caused problems with armv7 NEON code. If you file a PR with a test case, I am happy to take a quick look and try to fix

I've started using the strong PHI elimination pass, and it seems to work beautifully (producing much better placement of copy instructions) - though I'm seeing that it triggers an assert in debug+assert builds. The assertion is on line 1388 of RegisterCoalescer.C. Attached is the -debug output from the machine optimization part of the optimizer, for the simplest test case I could

I will try to make a standalone test case but the one that is failing uses a custom back end, so it's not really portable. So is the plan to have the strong PHI elimination behavior rolled into other passes? Andrew On 06/20/2012 06:54 PM, Cameron Zwarich wrote: > I'm the person who wrote it, and it's not really maintained, as we decided we wanted to go in a different direction

On Jun 7, 2012, at 10:54 PM, Hal Finkel wrote: > For example, sometimes LiveIntervals asserts with: > register: > %CTR8 > clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446: > void llvm::LiveInterval > s::handlePhysicalRegisterDef(llvm::MachineBasicBlock*, > llvm::MachineBasicBlock::iterator, llvm::SlotIndex, > llvm::MachineOperand&,

On Fri, 8 Jun 2012 08:49:32 -0700 Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Jun 7, 2012, at 10:54 PM, Hal Finkel wrote: > > > For example, sometimes LiveIntervals asserts with: > > register: > > %CTR8 > > clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446: > > void llvm::LiveInterval > >

On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > Predecessors according to CFG: BB#0 BB#1 > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 > %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12 > %vreg13<def> = BDNZ8 %vreg13,

On Thu, 7 Jun 2012 22:14:00 -0700 Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > > > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > > Predecessors according to CFG: BB#0 BB#1 > > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, > >

Hello again, I am trying to implement an optimization pass for PowerPC such that simple loops use the special "counter register" (CTR) to track the induction variable. This is helpful because, in addition to reducing register pressure, there is a combined decrement-compare-and-branch instruction BZND (there are also other related instructions). I started this process by converting the