similar to: [LLVMdev] GCC Merge Coming Up

Hello, Bill > This merge should go *much* more smoothly than the last merge -- it > could hardly be worse, right? ;-) I already did a test compile of > llvm-test with the patch and it compiled the programs without a > problem. Devang is currently testing it as well so that I have a > second opinion. One thing, which we already saw: please carefully check, that you won't

Nate, Right, okay. I was also planning on looking at what the assembly output generates and "emulating" its output. So I should be able to use the 'test/CodeGen/PowerPC' tests once I have augmented the MachO Writer PowerPC output. Does this seem like the right and sensible approach ? Aaron ----- Original Message ----- From: Nate Begeman To: LLVM Developers Mailing

Bill, Thanks for answering. To make sure that we are on the same page, let's agree on definitions :) Here, by fat binaries I mean the binary, where some functions are compiled for one flavor of x86, while others are compiled for another flavor of x86. I care about the usage model, which is important for LTO - a dispatch function (compiled for the least common denominator) + plus set of

Looking forward to these changes! Thanks for working on it. On Fri, Oct 11, 2013 at 10:32 PM, Bill Wendling <isanbard at gmail.com> wrote: > Hi Dmitry, > > I can try my best, but it would be a bit tricky to get it all finished by > then... > > -bw > > On Oct 11, 2013, at 4:10 AM, Dmitry Babokin <babokin at gmail.com> wrote: > > Bill, > > Are there

Bill, Are there any chances that you complete it before 3.4 is branched? On Thu, Oct 10, 2013 at 10:16 PM, Bill Wendling <isanbard at gmail.com> wrote: > On Oct 10, 2013, at 4:22 AM, Dmitry Babokin <babokin at gmail.com> wrote: > > > Bill, > > > > Thanks for answering. To make sure that we are on the same page, let's > agree on definitions :) Here, by

FYI: http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-October/066389.html Please read and let me know you comments. -bw On Oct 11, 2013, at 2:47 PM, Dmitry Babokin <babokin at gmail.com> wrote: > Looking forward to these changes! Thanks for working on it. > > > On Fri, Oct 11, 2013 at 10:32 PM, Bill Wendling <isanbard at gmail.com> wrote: > Hi Dmitry, > > I

Hi Dmitry, I can try my best, but it would be a bit tricky to get it all finished by then... -bw On Oct 11, 2013, at 4:10 AM, Dmitry Babokin <babokin at gmail.com> wrote: > Bill, > > Are there any chances that you complete it before 3.4 is branched? > > > On Thu, Oct 10, 2013 at 10:16 PM, Bill Wendling <isanbard at gmail.com> wrote: > On Oct 10, 2013, at

On Mon, Feb 23, 2009 at 2:19 PM, Nate Begeman <natebegeman at me.com> wrote: > > On Feb 23, 2009, at 1:46 PM, Chris Lattner wrote: > > In my opinion, the proper direction for shuffles is: >> >> 1. Back out your patch. >> 2. Move the functionality of "is splat" etc to method somewhere, e.g. >> on SDNode. >> 3. Introduce a new

On Feb 23, 2009, at 2:49 PM, Scott Michel wrote: > On Mon, Feb 23, 2009 at 2:19 PM, Nate Begeman <natebegeman at me.com> > wrote: > > On Feb 23, 2009, at 1:46 PM, Chris Lattner wrote: > > In my opinion, the proper direction for shuffles is: > > 1. Back out your patch. > 2. Move the functionality of "is splat" etc to method somewhere, e.g. > on

On Wed, Feb 15, 2006 at 02:53:05AM +0100, Jonas Gustavsson wrote: > I have been looking at the LLVM project for quite a bit but I was > wondering if there are any implication of using the project in a > commercial enviroment in terms of licensing restrictions and other > related issues, are there other people that use LLVM in a commecial > enviroment? LLVM's license is a

Hi Everyone! We are pleased to announce the impending checkin to CVS of the PowerPC / MachO backend for LLVM. Many thanks go out to all the LLVM developers for their help in making this happen. Misha Brukman and Chris Lattner will be handling the CVS integration in the near future. The PowerPC BE current compiles most of the testsuite correctly. There are known issues in C++, variable

On Oct 10, 2013, at 4:22 AM, Dmitry Babokin <babokin at gmail.com> wrote: > Bill, > > Thanks for answering. To make sure that we are on the same page, let's agree on definitions :) Here, by fat binaries I mean the binary, where some functions are compiled for one flavor of x86, while others are compiled for another flavor of x86. I care about the usage model, which is

Nadav, You are right, ISPC may issue intrinsics as a result of AST selection. Though I believe that we should stick to LLVM IR whenever is possible. Intrinsics may appear to be boundaries for optimizations (on both data and control flow) and are generally not optimizable. LLVM may improve over time from performance stand point and we would benefit from it (or it may play against us, like in this

On Oct 3, 2013, at 9:34 AM, Dmitry Babokin <babokin at gmail.com> wrote: > Bill, Ben, everyone, > > Some time ago "target-features" and "target-cpu" attributes were introduced. As I understand, they are intended to support generation of "fat binaries" (binaries with functions generated for different CPUs), particularly to support LTO compilation, when

Hi LLVMites! This patch adds the 'nobuiltin' attribute to to LLVM. This is needed during LTO, which right now ignores this attribute and command line flag. I want to make this an IR-level attribute instead of a target-dependent attribute because it's used during IR modification and not code generation. -bw -------------- next part -------------- A non-text attachment was scrubbed...

Bill, Ben, everyone, Some time ago "target-features" and "target-cpu" attributes were introduced. As I understand, they are intended to support generation of "fat binaries" (binaries with functions generated for different CPUs), particularly to support LTO compilation, when different source files have different targets (say, one of files should support SSE2, another

Hi Dmitry, Yes, this is a known problem with legalizing vector masks. The type <8 x i1> is legalized to 8 x i16, on SSE, but your operands are legalized to <4 x i32>. Type-legalization is performed per-node and we don’t have a good way to support instructions that mix the mask and operand type. Why does ISPC generate illegal vector types ? Does ISPC rely on the LLVM codegen to

In addition, there are groups at STMicroelectronics and at Siemens that have used or are considering using LLVM. Note that these are internal development projects for now -- they (and Apple) have not publicly announced products based on LLVM. --Vikram http://www.cs.uiuc.edu/~vadve http://llvm.cs.uiuc.edu/ On Feb 14, 2006, at 11:24 PM, Misha Brukman wrote: > On Wed, Feb 15, 2006 at

On Mon, Feb 23, 2009 at 8:26 PM, Chris Lattner <clattner at apple.com> wrote: > > On Feb 23, 2009, at 6:13 PM, Scott Michel wrote: > > On Mon, Feb 23, 2009 at 4:03 PM, Nate Begeman <natebegeman at me.com> wrote: > >> >> It's basically as Chris said; there will be a ShuffleVectorSDNode, and >> appropriate helper functions, node profile, and

Nadav, The problem appears only for vectors longer than available hardware register (in doubleword elements, i.e. more than 4 on SSE4 and more than 8 on AVX). Select does weird thing. <8 x i1> mask comes as two XMM registers, select converts them to a single XMM registers (i.e. 8 x 16 bit), immediately after it converts back to two XMM registers and does blend. Conversion forth and back has