similar to: [LLVMdev] Adapting created intrinsics to PowerPC backend

Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] Adapting created intrinsics to PowerPC backend"

2008 May 07
2
[LLVMdev] Creation of Intrinsics with Pointer Return Types
<table cellspacing='0' cellpadding='0' border='0' ><tr><td style='font: inherit;'>Hi,<br>I tried creating intrinsics which are to be<br>placeholders for a set of instructions (actually a section of a basic block) to be executed elsewhere(for e.g. in HW).<br>These intrinsics are to take care of the data dependencies of the set of
2008 May 07
0
[LLVMdev] Creation of Intrinsics with Pointer Return Types
Hello, LLVM's intrinsic overloading mechanism does not currently support overloading on pointer types. Patches to implement this would be welcome. Dan On May 7, 2008, at 9:25 AM, aditya vishnubhotla wrote: > Hi, > I tried creating intrinsics which are to be > placeholders for a set of instructions (actually a section of a > basic block) to be executed elsewhere(for e.g. in
2008 Aug 22
3
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
No, I don't. Cheers, Gary Dale Johannesen wrote: > This looks OK to check in, do you have write access? > > On Aug 21, 2008, at 6:38 AMPDT, Gary Benson wrote: > > >Dale Johannesen wrote: > >>On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote: > >>>I'm trying to implement llvm.memory.barrier on PowerPC. I've > >>>modelled my patch
2008 Aug 19
2
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
Hi all, I'm trying to implement llvm.memory.barrier on PowerPC. I've modelled my patch (attached) on the implementation in X86, but when I try and compile my test file (also attached) with llc I get the error "Cannot yet select: 0x10fa4ad0: ch = MemBarrier 0x10fa4828, 0x10fa4c68, 0x10fa4be0, 0x10fa4be0, 0x10fa4be0, 0x10fa4be0". This presumably means my "membarrier"
2008 Aug 21
2
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
Dale Johannesen wrote: > On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote: > > I'm trying to implement llvm.memory.barrier on PowerPC. I've > > modelled my patch (attached) on the implementation in X86, but > > when I try and compile my test file (also attached) with llc I > > get the error "Cannot yet select: 0x10fa4ad0: ch = MemBarrier > >
2008 Feb 19
2
[LLVMdev] Problem with variable argument intrinsics
Hi, I tried creating variable argument intrinsics which are to be placeholders for some instructions which should not be executed by the backend. Kindly help me with the errors in my "migrate_begin" intrinsic creation //Additions made to Intrinsics.td file: def llvm_migrate_begin : LLVMType<iAny>; def int_migrate_begin :
2008 Feb 20
1
[LLVMdev] Invalid intrinsic name error
Hi, Thank You for the advice and we were able to solve that problem by the following modifications to the Instrinsics.td file. But I now have an "Invalid Intrinsic name" error This error occurs presumably because the created intrinsic is named: llvm.migrate_begin.i32 Intrinsics.gen checks for a string length of 18 (i.e. the length without the .i32). Kindly help me through it.
2008 Feb 19
0
[LLVMdev] Problem with variable argument intrinsics
On Feb 19, 2008, at 1:11 AM, aditya vishnubhotla wrote: > Hi, > I tried creating variable argument intrinsics which > are to be placeholders for some instructions which > should not be executed by the backend. > > Kindly help me with the errors in my "migrate_begin" > intrinsic creation > > //Additions made to Intrinsics.td file: > > def
2008 Aug 21
0
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote: > Hi all, > > I'm trying to implement llvm.memory.barrier on PowerPC. I've modelled > my patch (attached) on the implementation in X86, but when I try and > compile my test file (also attached) with llc I get the error "Cannot > yet select: 0x10fa4ad0: ch = MemBarrier 0x10fa4828, 0x10fa4c68, > 0x10fa4be0,
2008 Mar 04
0
[LLVMdev] Deleting Instructions after Intrinsic Creation
Hi, I tried creating intrinsics which are to be placeholders for a set of instructions which should not be executed by the backend. I want to retain only intrinsic,phi and terminator instructions in a basic block. I have taken care of the external dependencies of basic block. How do I delete the rest of the instructions? Thank You Aditya P.S:
2008 Aug 21
0
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
This looks OK to check in, do you have write access? On Aug 21, 2008, at 6:38 AMPDT, Gary Benson wrote: > Dale Johannesen wrote: >> On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote: >>> I'm trying to implement llvm.memory.barrier on PowerPC. I've >>> modelled my patch (attached) on the implementation in X86, but >>> when I try and compile my test
2008 Mar 04
1
[LLVMdev] Deleting Instructions after Intrinsic Creation
Hi, I tried creating intrinsics which are to be placeholders for a set of instructions which should not be executed by the backend. I want to retain only intrinsic,phi and terminator instructions in a basic block. I have taken care of the external dependencies of basic block. How do I delete the rest of the instructions? Thank You Aditya P.S:
2008 Aug 22
0
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
OK, I've checked it in for you, thanks. Please do contact Chris about write access. On Aug 22, 2008, at 12:38 AMPDT, Gary Benson wrote: > No, I don't. > > Cheers, > Gary > > Dale Johannesen wrote: >> This looks OK to check in, do you have write access? >> >> On Aug 21, 2008, at 6:38 AMPDT, Gary Benson wrote: >> >>> Dale Johannesen
2008 Feb 12
0
[LLVMdev] Inrinsic Creation Problem
Hi, I tried creating intrinsics which are to be placeholders for some instructions which should not be executed by the backend. Kindly help me with the errors in my "migrate_begin" intrinsic creation The following are the additions made to the Intrinsics.td file def llvm_migrate_begin : LLVMType<iAny>; def int_migrate_begin : Intrinsic<[llvm_migrate_begin,llvm_vararg_ty],
2007 Dec 20
4
[LLVMdev] First time!
Hi! I want to know How to count the number of predecessors for each basic block? Thank You ____________________________________________________________________________________ Never miss a thing. Make Yahoo your home page. http://www.yahoo.com/r/hs
2007 Jan 14
0
[LLVMdev] Inserting an assembly instruction in the calling sequence of the powerpc target
On Fri, 12 Jan 2007, Nicolas Geoffray wrote: > I'm currently implementing a linux/ppc target in llvm. The abis between cool > Darwin/ppc and linux/ppc are different and I'm running into problems > with vararg calls. ok > Before a variadic method is called, an extra instruction must be > executed (which is creqv 6, 6, 6). This instruction is not necessary in >
2007 Jan 12
2
[LLVMdev] Inserting an assembly instruction in the calling sequence of the powerpc target
Hi all, I'm currently implementing a linux/ppc target in llvm. The abis between Darwin/ppc and linux/ppc are different and I'm running into problems with vararg calls. Before a variadic method is called, an extra instruction must be executed (which is creqv 6, 6, 6). This instruction is not necessary in Darwin/ppc. I looked into the PowerPC target implementation and the code generation
2007 Dec 20
0
[LLVMdev] First time!
Hi aditya, There are two ways to cound the number of predecessors for each basic block. You can generate the control flow graph using the CallGraphScc pass with the granularity of basic block and can simply traverse the graph bottom up till the root. The number of nodes encountered would be the number of predecessors. The second way would be to use the special ;preds marker in the llvm IR. Each
2012 May 23
1
[LLVMdev] tblgen for generation of Haskell bindings to LLVM intrinsics
I want to generate Haskell bindings to LLVM intrinsics. In a first attempt I wrote a little parser that reads IntrinsicsX86.td and outputs a Haskell module. E.g. the definition def int_x86_avx_max_ps_256 : GCCBuiltin<"__builtin_ia32_maxps256">, Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty], [IntrNoMem]>; is turned into
2020 Sep 29
3
TableGen processing of target-specific intrinsics
Each of the main TableGen files for the supported targets includes include "llvm/Target/Target.td" In turn, Target.td includes include "llvm/IR/Intrinsics.td" The final lines of Instrinsics.td are include "llvm/IR/IntrinsicsPowerPC.td" include "llvm/IR/IntrinsicsX86.td" include "llvm/IR/IntrinsicsARM.td" include