similar to: [LLVMdev] ctpop intrinsic question

Hello. Could you please tell me why am I not able to recognize (with LLVM built from the SVN code in Apr 25, 2018) the LLVM IR intrinsic ctpop (described at https://llvm.org/docs/LangRef.html#llvm-ctpop-intrinsic) in the following program: int PopCnt_Simple(int x) { int numBits = 0; int i; //for (i = 0; i < 32; i++) { for (i = 0; x !=

Hi, Following is excerpted from http://llvm.org/releases/3.1/docs/LangRef.html#int_ctpop. How come the return type needs to be consistent with parameter type? i64/i128 seems to be overkill, and i8, i16 are inconvenient. ----------------------------------- declare i8 @llvm.ctpop.i8(i8 <src>) declare i16 @llvm.ctpop.i16(i16 <src>) declare i32 @llvm.ctpop.i32(i32

On 1/18/2018 12:57 AM, ORiordan, Martin via llvm-dev wrote: > Quick question. The 'ISD::CTPOP' node allows a target to lower the counting of ones in a word to a single instruction. Our target also has an instruction for counting the zeroes in a word. Does CTPOP support counting of zeroes as well as ones instead of doing either "CTPOP(INVERT(operand))" or "N-bits -

Quick question. The 'ISD::CTPOP' node allows a target to lower the counting of ones in a word to a single instruction. Our target also has an instruction for counting the zeroes in a word. Does CTPOP support counting of zeroes as well as ones instead of doing either "CTPOP(INVERT(operand))" or "N-bits - CTPOP(operand)"? Thanks, MartinO

LLVM appears to support Library functions for ISD::SRA ,ISD::SHL, and ISD::SRL, as they are properly defined in RuntimeLibCalls.def. The library functions defined in RuntimeLibCalls.def (among others) are these: HANDLE_LIBCALL(SRA_I16, "__ashrhi3") HANDLE_LIBCALL(SRA_I32, "__ashrsi3") HANDLE_LIBCALL(SRA_I64, "__ashrdi3") However, setting

Hi Eli, Thanks for pointing to the CTLZ_ZERO_UNDEF “LibCall” implementation. I have not it in the version that I am currently using, so it’s nice to know that it’s implemented now. Incidentally, the CTLZ… implementation is IDENTICAL to what I am proposing for the Shifts. This is not just adding support for “out-of-tree-targets”, but giving consistency to the fact that we have perfectly defined

Developers, As part of PR411, I have made several of the intrinsic functions non- overloaded. While the assembler and bytecode reader are backwards compatible, front-end writers should start using the non-overloaded versions of the intrinsics. The llvm-gcc has already been updated to generate the new intrinsic names. Other front-ends will start seeing warnings about the names of intrinsics that

I am new to the LLVM backends, I am wondering how instruction selection is done in LLVM backends, I looked at the .td files in Target/X86, they all seem to be small and do not deal with common X86 instructions, i.e. mov, push, pop, etc. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

<div> </div><div><div><p>Carry-less multiplication[1] instructions exist (at least optionally) on many architectures: armv8, RISC-V, x86_64, POWER, SPARC, C64x, and possibly more.</p><p>This proposal is to add a <code>llvm.clmul</code> instruction. Or if that is contentious, <code>llvm.experimental.bitmanip.clmul</code> instruction.

05.07.2020, 05:22, "Roman Lebedev" <lebedev.ri at gmail.com>: > On Sun, Jul 5, 2020 at 12:18 PM Shawn Landden via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >>  Carry-less multiplication[1] instructions exist (at least optionally) on many architectures: armv8, RISC-V, x86_64, POWER, SPARC, C64x, and possibly more. >> >>  This proposal is to add a

Hi Eli, First of all, please I would appreciate that you try to not confuse my limited use of English with stupidity or lack or criteria in other subjects. I’m not English native, so please keep that in mind. You have been significantly helpful in the recent past so please keep on. Interestingly, you made a mention of a related but not identical issue. It is true that most (or all) processors

Hi Chris, > Of interest may be this thesis. It talks about converting alpha code > to LLVM (among other things): > http://llvm.org/pubs/2004-05-JoshiMSThesis.html Thanks, it was of interest. I didn't spot its relevance from the title. Cheers, Ralph.

Per subject, this patch adding an additional pass to handle vector operations; the idea is that this allows removing the code from LegalizeDAG that handles illegal types, which should be a significant simplification. There are still some issues with this patch, but does the approach look sane? -Eli -------------- next part -------------- Index: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Chris Lattner wrote: > On Mon, 30 Jul 2007, Sarah Thompson wrote: > >> ... can *any* instruction(s) other than load and store cause memory >> reads or writes? >> > > Functions calls can (transitively), This isn't a problem because I'll be picking up those reads and writes as the function executes anyway. > intrinsics can, Would it be feasible to

On Wed, May 16, 2018 at 11:27 AM, Manuel Jacob <me at manueljacob.de> wrote: > On 2018-05-16 00:34, Sanjay Patel via llvm-dev wrote: > >> Vectorization goes overboard because the throughput cost model used by the >> vectorizers doesn't match the 6 IR instructions that correspond to 1 x86 >> rotate instruction. Instead, we have: >> >> [...] >>

Hello, I'd like to do some initial experiments with LLVM on embedded ARM (Nokia N800), but ran into a build issue. Could s.o. give me a tip? Thx alot, Tobias P.S.: just as sidenote, LLVM 2.2 builds cleanly on GCC 4.2.3 / Linux. === I'm building on Ubuntu/Scratchbox/ARMEL using GCC 3.4.4 (CodeSourcery ARM 2005q3-2) using ./configure --prefix=$HOME/local/llvm-2.2 --enable-jit

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

On 2018-05-16 00:34, Sanjay Patel via llvm-dev wrote: > Vectorization goes overboard because the throughput cost model used by > the > vectorizers doesn't match the 6 IR instructions that correspond to 1 > x86 > rotate instruction. Instead, we have: > > [...] > > The broken cost model also affects unrolling and inlining. Size costs > are > overestimated

(As per IRC discussion) I understand that the carry-less multiplication algorithm has it's uses since/and it is implemented as an instruction in many architectures and that adding it as a general-purpose intrinsic will allow us to drop target-specific intrinsics as by-product. What i do *NOT* understand is: what is the actual/main goal/driving factor of adding an LLVM intrinsic for it? The