similar to: [LLVMdev] Handling "adde" nodes !!

We've used the used attribute to ensure they are not deleted and had no problem. Andrew On Tue, Jul 21, 2009 at 10:07 AM, <Sanjiv.Gupta at microchip.com> wrote: > Hi, > Apparently, there is no explicit support for ISRs in the llvm framework.  I > could not find a matching attribute that can be used to mark a function as > an ISR, which codegen and optimizer can use

Hi, Apparently, there is no explicit support for ISRs in the llvm framework. I could not find a matching attribute that can be used to mark a function as an ISR, which codegen and optimizer can use accordingly. ISRs aren't called explicity from any function, so currently the optimizer deletes them. We are planning to introduce a new "interrupt" attribute (to be modeled similiar to

Chris Lattner wrote: > On Feb 9, 2010, at 7:39 PM, Sanjiv Gupta wrote: > > >> Hi, >> I need to add switches like -disable-mem2reg, disable-gvn to llvm-ld. >> Currently CreateStandardLTOPasses takes in only DisableInternalize and >> DisableInliner switches. >> >> Is modifying this API okay for these new switches, or is it doable in >> some

On Oct 1, 2008, at 3:01 AM, sanjiv gupta wrote: > On Wed, 2008-10-01 at 11:12 +0200, Duncan Sands wrote: >> Hi, >> >>> I have another query related to type legalizer. >>> Can a target ignore certain nodes during legalize? Probably a hook >>> for >>> target that can be called inside IgnoreNodeResults ()? >> >> while this could be

Why can't I custom lower ADDE operation for legal types? Our target does not have an add with carry instruction. We check the carry bit in status register and add 1 to the result if it is set. -Sanjiv

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On Thu, 2008-10-02 at 08:53 -0700, Chris Lattner wrote: > On Oct 2, 2008, at 8:38 AM, Eli Friedman wrote: > > > On Thu, Oct 2, 2008 at 7:34 AM, Evan Cheng <evan.cheng at apple.com> > > wrote: > >> > >> On Oct 2, 2008, at 2:01 AM, sanjiv gupta wrote: > >> > >>> > >>>> > >>>> So you have a i16 register

On Wed, 2008-10-01 at 11:12 +0200, Duncan Sands wrote: > Hi, > > > I have another query related to type legalizer. > > Can a target ignore certain nodes during legalize? Probably a hook for > > target that can be called inside IgnoreNodeResults ()? > > while this could be done, I don't like the idea of doing an end-run > around the whole type legalization

All the sub methods called inside ExpandIntegerOperand like ExpandInOp_STORE etc have access to the expanded operands map. Why they aren't passed to target LowerOperation? A target may also want to use the already expanded Lo and Hi parts. - Sanjiv -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Sun, 2008-10-19 at 23:18 -0700, Evan Cheng wrote: > > On Oct 18, 2008, at 7:01 AM, sanjiv gupta wrote: > > > On Thu, 2008-10-16 at 08:55 -0700, Evan Cheng wrote: > > > On Oct 15, 2008, at 11:21 AM, sanjiv gupta wrote: > > > > > > > > > > > > > > > > > > > Ok. The AX / AH super-reg and sub-reg relationship is

> > So you have a i16 register class which makes the type legal. You can > make loads and stores legal (can you?). But you will have to custom > lower all other i16 operations. This will work, but it requires a lot > of target specific code. True. If we add the i16 reg class we will need to write a lot of target specific code. To avoid that our idea was not to tell the

On Mon, 2008-10-20 at 08:07 -0700, Evan Cheng wrote: > On Oct 20, 2008, at 7:10 AM, sanjiv gupta wrote: > > >>> > >>> PR2916 filed. > >>> Though I did not quite understand why this could be a tablegen bug? > >> > >> > >> Based on your comments. :-) It should be possible to specify two FSR0 > >> sub-registers (FSR0L,

Pointer size on our target is 16-bits, and we have two 16-bit registers that can be used only to hold pointers (indirect addresses). All operations on the target are 8-bit operations, so it takes two 8-bit loads to load these pointer registers. We want LLVM to automatically expand all types to 8-bit values. The problem is that LLVM does not expand GlobalAddresses, which are 16-bit

On Oct 20, 2008, at 7:10 AM, sanjiv gupta wrote: >>> >>> PR2916 filed. >>> Though I did not quite understand why this could be a tablegen bug? >> >> >> Based on your comments. :-) It should be possible to specify two FSR0 >> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the >> workaround you described: >> >>

> > On Tue, Sep 30, 2008 at 9:48 AM, <Sanjiv.Gupta at microchip.com> wrote: > > All the sub methods called inside ExpandIntegerOperand like > ExpandInOp_STORE > > etc have access to the expanded operands map. > > > > Why they aren't passed to target LowerOperation? A target may also want > to > > use the already expanded Lo and Hi parts. >

Hi Duncan, We are targetting a reasonably functional PIC16 backend for llvm 2.5. The only problem in our way is a local patch in ExpandIntegerOperand, which couldn't make its way to trunk so far. The discussion is contained in the following link: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20081103/069593.html I now have time to take it up again and do whatever rework is

On Thu, Oct 2, 2008 at 7:34 AM, Evan Cheng <evan.cheng at apple.com> wrote: > > On Oct 2, 2008, at 2:01 AM, sanjiv gupta wrote: > >> >>> >>> So you have a i16 register class which makes the type legal. You can >>> make loads and stores legal (can you?). But you will have to custom >>> lower all other i16 operations. This will work, but it

On Tue, Sep 30, 2008 at 9:48 AM, <Sanjiv.Gupta at microchip.com> wrote: > All the sub methods called inside ExpandIntegerOperand like ExpandInOp_STORE > etc have access to the expanded operands map. > > Why they aren't passed to target LowerOperation? A target may also want to > use the already expanded Lo and Hi parts. You don't really need access to the map; just

On Wed, 2008-10-15 at 10:08 -0700, Evan Cheng wrote: > On Oct 15, 2008, at 5:29 AM, sanjiv gupta wrote: > > > On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote: > >> You need to specify sub-register == super-register, idx relationship. > >> See X86RegisterInfo.td: > >> > >> def x86_subreg_8bit : PatLeaf<(i32 1)>; > >> def

Legalizer will expand arithmetics using addc and adde. Is it not working for you? It works fine on x86, you can take a look how it's done. Evan On Sep 8, 2008, at 4:03 AM, Richard Pennington wrote: > My target doesn't support 64 bit arithmetic, so I'd like to supply > definitions for adde/addc. The problem is I can't seem to figure out > the > magic. Here's