Displaying 20 results from an estimated 2000 matches similar to: "[LLVMdev] Classifying Operands & Def/Use Chains"
2008 Jan 11
0
[LLVMdev] Classifying Operands & Def/Use Chains
On Jan 11, 2008, at 2:00 PM, David Greene wrote:
> Is there any way to discover whether a particular operand of a
> MachineInst
> participates in addressing? That is, if the MachineInst references
> memory,
> can I tell, given an operand, whether that operand is part of the
> address
> calculation for the instruction?
Nope, not that I know of.
> Also, is there any
2008 Jan 11
1
[LLVMdev] Classifying Operands & Def/Use Chains
On Friday 11 January 2008 16:36, Chris Lattner wrote:
> On Jan 11, 2008, at 2:00 PM, David Greene wrote:
> > Is there any way to discover whether a particular operand of a
> > MachineInst
> > participates in addressing? That is, if the MachineInst references
> > memory,
> > can I tell, given an operand, whether that operand is part of the
> > address
>
2011 May 02
2
[LLVMdev] LiveVariables not updated in MachineBasicBlock::SplitCriticalEdge?
Is LiveVariables updated correctly when TII->RemoveBranch and
TII->InsertBranch are called in the following piece of code?
- MachineBasicBlock::updateTerminator() line 307 of MachineBasicBlock.cpp:
if (FBB) {
// The block has a non-fallthrough conditional branch. If one of its
// successors is its layout successor, rewrite it to a fallthrough
// conditional branch.
2011 May 03
0
[LLVMdev] LiveVariables not updated in MachineBasicBlock::SplitCriticalEdge?
On May 2, 2011, at 3:51 PM, Akira Hatanaka wrote:
> - vreg81's VarInfo:
> Alive in blocks: 5, 6, 7, 8, 10, 12, 13, 19,
> Killed by:
> #0: J <BB#17>
>
>
> As you can see, VarInfo vreg81 is killed by the unconditional jump instruction of BB#20 when it should be killed by the newly created conditional branch in BB#14 (BEQ). Is this a bug in
2005 Sep 07
1
[LLVMdev] LiveIntervals invalidates LiveVariables?
On 08/09/05, Alkis Evlogimenos <evlogimenos at gmail.com> wrote:
> to those coalesced registers, it is logical that noone will ever query
> the liveness of those registers (unless there is a bug somewhere in the
Indeed the coalesced registers may logically not be queried since they
do not appear in any operand list of the machine code, but the
VarInfo::DefInst in VirtRegInfo of the
2005 Sep 07
3
[LLVMdev] LiveIntervals invalidates LiveVariables?
I though LiveVariables may be invalidated by LiveIntervals, but it's
declared not:
void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
{
AU.addPreserved<LiveVariables>();
AU.addRequired<LiveVariables>();
...
LiveInterval may coalesce virtual registers and remove identity moves
instructions:
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
2005 Sep 07
0
[LLVMdev] LiveIntervals invalidates LiveVariables?
On Wed, 2005-09-07 at 18:24 +0800, Tzu-Chien Chiu wrote:
> I though LiveVariables may be invalidated by LiveIntervals, but it's
> declared not:
>
> void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
> {
> AU.addPreserved<LiveVariables>();
> AU.addRequired<LiveVariables>();
> ...
>
> LiveInterval may coalesce virtual registers and
2015 Feb 11
2
[LLVMdev] deleting or replacing a MachineInst
I'm writing a peephole pass and I'm done with the X86_64 instruction level
detail work. But I'm having difficulty with the basic block surgery
of replacing the old MachineInst.
The peephole pass gets called per MachineFunction and then iterates over
each MachineBasicBlock and in turn over each MachineInst. When it finds an
instruction which should be replaced, it builds a new
2005 May 17
2
[LLVMdev] Register Allocation problem
Ok, i'm having a problem with understanding the allocating of registers.
I've written in the "addPassesToEmitAssembly()" the passes to create
the assembly code, as in the PowerPC example. I'ved tried filling up as
much of the code in <Target>RegisterInfo.cpp (Register/Frame code) to
handle writing and reading from stack.
The allocation method I used was
2014 Sep 25
2
[LLVMdev] MachineRegisterInfo use_iterator/reg_iterator?
Hi folks,
I would like to find out the machine instructions that use some given registers in the reverse order, and I came across these iterators (use_iterator/reg_iterator). However, there are two things I noticed:
1) These iterators seem to traverse the machine function a bit differently from what I get from the machine function dump. In other words, the use_iterator list is not constructed in
2014 Sep 25
2
[LLVMdev] MachineRegisterInfo use_iterator/reg_iterator?
Thanks Quentin. I'm trying to examine from the operands of the return
instruction, and then to get the last assignment of those. I thought
use_iterator/reg_iterator may suit better than just loop through the
machine basicblock in the reverse order.
Cheng-Chih
On Thu, Sep 25, 2014 at 1:51 PM, Quentin Colombet <qcolombet at apple.com>
wrote:
> Hi Cheng-Chih,
>
> On Sep 25,
2005 May 17
0
[LLVMdev] Register Allocation problem
On Mon, May 16, 2005 at 05:15:30PM -0700, John Cortes wrote:
> If I use any of the regalloc parameters (local, ...) I get an error in
> the LiveVariable.cpp file, in the part that I think cheaks for dead
> code because a Variable didn't have a defined Instance to a Machine
> instruction.
>
> " llc: LiveVariables.cpp:86: void
>
2015 Jan 22
3
need help with renaming a variable
Hello.
I am new to R, so my question/problem might be very basic, but I cannot
figure out how to solve it.
So, I would really appreciate your help.
I would like to rename a variable in a very large file (181GB) called
"2013.xdf" that is saved on my external hard drive.
I tried running the following code to rename variable # 2 in the file and
save this change, which produced some
2020 Oct 06
2
Optimizing assembly generated for tail call
Hello,
I recently found that LLVM generates sub-optimal assembly for a tail call
optimization case. Below is an example (https://godbolt.org/z/ao15xE):
> void g1();
> void g2();
> void f(bool v) {
> if (v) {
> g1();
> } else {
> g2();
> }
> }
>
The assembly generated is as follow:
> f(bool): # @f(bool)
> testb %dil, %dil
> je .LBB0_2
>
2005 Sep 20
2
[LLVMdev] Requiring LiveIntervals
One of my pass requires LiveIntervals to build the interference graph,
because LiveVariables do not provide an interface to iterate through
all viritual registers. But LiveIntervalAnalysis.h is not in
"include/llvm/CodeGen", so I have to either include it by:
#include "../../llvm/lib/CodeGen/LiveIntervalAnalysis.h"
or point my project include path to
2012 Apr 19
3
[LLVMdev] def-use chains and use-def chains
Hi,
I need to find out all the places where the value of a variable is being
used. For this I have to implement reaching definitions(def-use chains).
When I searched for its implementation I found Iterating over def-use &
use-def chains <http://llvm.org/docs/ProgrammersManual.html#iterate_chains>.
will this work for finding the places where a variable is reaching?
I tried to use
2005 Sep 20
0
[LLVMdev] Requiring LiveIntervals
On Tue, 20 Sep 2005, Tzu-Chien Chiu wrote:
> One of my pass requires LiveIntervals to build the interference graph,
Ok.
> because LiveVariables do not provide an interface to iterate through
> all viritual registers.
Ok, you could add a method to LiveVariables that returns
VirtRegInfo.size(). The virtual registers are defined by the range:
[MRegisterInfo::FirstVirtualRegister,
2011 May 03
1
[LLVMdev] LiveVariables not updated in MachineBasicBlock::SplitCriticalEdge?
Does updateTerminator() need to be rewritten in order to implement the
changes you suggested (call LV->replaceKillInstruction)? Or can it be taken
care of just by adding code to the files in Target/Mips?
Also, is the generated code still correct if
-disable-phi-elim-edge-splitting is added to the command line options?
On Mon, May 2, 2011 at 5:00 PM, Jakob Stoklund Olesen <stoklund at
2005 Sep 20
2
[LLVMdev] Requiring LiveIntervals
On 20/09/05, Chris Lattner <sabre at nondot.org> wrote:
> > because LiveVariables do not provide an interface to iterate through
> > all viritual registers.
>
> Ok, you could add a method to LiveVariables that returns
> VirtRegInfo.size(). The virtual registers are defined by the range:
> [MRegisterInfo::FirstVirtualRegister,
>
2012 Apr 20
0
[LLVMdev] def-use chains and use-def chains
Hi Duncan Sands,
I frankly don't know what a variable gets converted to (SSA register or
memory chunk). What I meant is, for example
I1: int i, j=10; I2: scanf("%d", &j); I3: i = j + 1;
Here I want to know whether the value of j in I1 reaches I3 or not.
Best Regards,
Srikanth Vaindam
you didn't define what you mean by a variable. LLVM has virtual registers
which
are