similar to: [LLVMdev] Help with citation

Guys, I need advice in how to handle a problem. The problem: In X86_64, pointers are 64-bit variables, and are stored into 64-bit registers. However, some pointers are small enough that they can be represented as 32-bit values. Is there some way, in LLVM, to recognize which pointers can be stored into 32-bit registers, and so modify their class accordingly? Any ideas or hints would

Hi Florian, we though about using UIUC, like in LLVM. Do you guys know if that could be a problem, given that we are mining the functions from github? > Have you thought about integrating the benchmarks as external tests into LLVM’s test-suite? That would make it very easy to play around with. We did not think about it actually. But we would be happy to do it, if the community accepts

On Thu, May 15, 2008 at 5:45 PM, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > Guys, I need advice in how to handle a problem. > > The problem: > In X86_64, pointers are 64-bit variables, and are stored into 64-bit > registers. However, some pointers are small enough that they can be > represented as 32-bit values. > Is there some way, in

On 11/23/07, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > Hi, Sanjiv, > > those passes operate on the whole machine function. Each machine > function contains many basic blocks. If a program has many functions, the > register allocator will be called as many times, i.e it does not do > interprocedural allocation. > > best, > >

Dear guys, I want to coalesce some copies, and I would like to know if there is any method that I can call, like JoinCopy from the old (LLVM 1.9) LiveIntervals class. I found it in SimpleRegisterCoalescing (LLVM 2.1), but I do not want to call this analysis, as I have my own. basically, I can determine that two virtuals do not overlap, and I know that it is safe to join them. In

I'm just starting to dive into llvm, hoping to implement a good graph coloring register allocator. I gather that this has been discussed before. What is the RegAllocGraphColoring.cpp currently in the sources? It seems to be the Fred Chow algorithm but it's not mentioned in the documentation anywhere. Does it work? -Dave

>> And I have a quite fast algo that I believe is simpler than [Budimlic02] >> and I can share it with you :) > > Do you have a paper on this? I'd be interested in seeing it. > Yes, I have a tech report on this page: http://compilers/fernando/projects/soc/ and I have submitted a paper to SAS, and now I am waiting for the review. The coalescing algorithm is described in

> And I have a quite fast algo that I believe is simpler than [Budimlic02] > and I can share it with you :) Do you have a paper on this? I'd be interested in seeing it. -Tanya > > Fernando > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >

On 4/3/07, David Greene <greened at obbligato.org> wrote: > > I'm just starting to dive into llvm, hoping to implement a > good graph coloring register allocator. I gather that this > has been discussed before. > > What is the RegAllocGraphColoring.cpp currently in the > sources? It seems to be the Fred Chow algorithm but > it's not mentioned in the

Hi guys, I have been using a debugger for my register allocator. The debugger happened to be very useful at catching register assignment errors. I've put the debugger on-line, if anyone who is working with register allocation wants to use. The debugger itself has nothing to do with LLVM, but I've coded a spiller that prints the code in a format that the debugger can read. The

Hi, again, I think you can do it in the same way that the other allocators have been coded, i.e extend RA, register the pass and so forth. I am not sure about the best way to pass information among a run of RegAlloc to the other, maybe the other guys in the list could suggest something. Yet, you can always dump it into a file, and read it again, everytime it is necessary. Remember that

Hey, guys, I am creating some move instructions with MRegisterInfo::copyRegToReg. How do I get a pointer to the instruction that I just created? Is there a way to do something like: // mbb is MachineBasicBlock, reg_info is MRegisterInfo MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); reg_info->copyRegToReg(mbb, iter, dst, src, rc); iter--; (???) MachineInstr *

Guys, I am in need of a no-op instruction: an instruction that does not do anything, and has no operands. Does LLVM predefine such an instruction? I want to transform the program so that there is no empty basic block. Fernando

Thanks again. One more question here: Since the regalloc works once per function, do I stil have access to the Call graph? Just saving information between regalloc passes for different functions may not be enough for my case. I will need to maintain the regalloc info of various passes in the call graph order. Anyways thanks for your inputs. I will get back if I need to learn more. Sanjiv On Nov

Dear guys, what is the best way to implement a swap of floating point registers in X86? For the integer registers, I am using xchg. Is there a similar instruction for floating point? My function to insert swaps is like: void X86RegisterInfo::swapRegs( MachineBasicBlock & mbb, MachineBasicBlock::iterator mi, unsigned r1, unsigned r2, const TargetRegisterClass

Hey guys, I am trying to speed up some of my LLVM/llc passes. Is there a way to use something like gprof on llc? If not, do you guys know anything that I can use to discover which routines of my passes are taking most of the time? thanks, Fernando

Hi, guys, What is the opcode of the instruction to swap two registers in X86? After updating my LLVM branch, I realized that there is no longer an opcode for xchg with two register operands in X86GenInstrNames.inc. I found only instructions to swap memory and registers: XCHG16rm, XCHG32rm, XCHG64rm and XCHG8rm. I am updating from LLVM 2.1 to current trunk. The names that I was

Dear LLVMers, we, at UFMG, have been building a large collection of compilable benchmarks. Today, we have one million C files, mined from open-source repositories, that compile into LLVM bytecodes (and from there to object files). To ensure compilation, we perform type inference on the C programs. Type inference lets us replace missing dependencies. The benchmarks are available at:

Dear llvmers, I am trying to insert a move instruction where both source and destination registers are physical registers. How is the code for this? I tried this one here: void PhiDeconstruction_Fer::add_move ( MachineFunction & mf, MachineBasicBlock & mbb, unsigned

I would like to make a suggestion. In the LiveIntervalAnalysis class, instead of numbering the instructions in the order in which basic blocks are stored in the machine function, use the df_ext_iterator. It will order the instruction according to the dominance tree (or it seems to be doing so). There are many advantages in doing this. One of them is that, once you traverse the dominance tree