similar to: [LLVMdev] allocating registers less "sparingly"

On Nov 5, 2007, at 2:55 AM, Pekka Jääskeläinen wrote: > Hello LLVM people, > > Our customizable TTA target [1] is capable of having plenty of > registers > and register file ports to improve instruction level parallelism and > reduce spills. It's totally up to the designer of the particular TTA > processor how much the processor has registers and register file >

On Nov 5, 2007, at 2:55 AM, Pekka Jääskeläinen wrote: > Hello LLVM people, > > Our customizable TTA target [1] is capable of having plenty of > registers > and register file ports to improve instruction level parallelism and > reduce spills. It's totally up to the designer of the particular TTA > processor how much the processor has registers and register file >

Hello, Attached is a trivial patch to increase the max number of physical registers in LLVM from 1024 to 16384. In our TCE toolset we allow the designer to choose the number of registers in the designed TTA processors freely, and recently while experimenting with using TTA for a GPU design we have bumped into this limit several times. What has made matters a bit worse for us is that we need to

Hi all, I think this master's thesis from our group could be of interest. It describes the "bridge" between the LLVM codegen and our custom TTA codegen in TCE: a runtime retargetable architecture description file driven LLVM compiler backend. The thesis might be useful also for people implementing backends for LLVM in general. http://tce.cs.tut.fi/doc/Compiler.pdf If you have any

Hello, Can someone please commit this patch? Thanks. On 11/21/2009 11:15 PM, Pekka Jääskeläinen wrote: > Hello, > > Attached is a trivial patch to increase the max number of physical > registers in LLVM from 1024 to 16384. > > In our TCE toolset we allow the designer to choose the number of > registers in the designed TTA processors freely, and recently > while

TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). TTA is a minimalistic processor architecture template that allows high level of control for the designer to choose the boundary between the hardware and the software. The toolset provides a complete codesign flow from C programs down to

Hi, On 06/18/2011 06:26 AM, Benjamin Müller wrote: > i created a Function Pass to retrieve the Control/Data Flow Graph from > a simple program, > now i would like to statically schedule the Instructions. Is this > possible by starting to modify the SelectionDAG Files ? > Or can i even build a "standalone" custom scheduler? > Thank you very much for any tipps. You

Hi there, i created a Function Pass to retrieve the Control/Data Flow Graph from a simple program, now i would like to statically schedule the Instructions. Is this possible by starting to modify the SelectionDAG Files ? Or can i even build a "standalone" custom scheduler? Thank you very much for any tipps. Ben

On Nov 21, 2009, at 1:15 PM, Pekka Jääskeläinen wrote: > Hello, > > Attached is a trivial patch to increase the max number of physical > registers in LLVM from 1024 to 16384. > > In our TCE toolset we allow the designer to choose the number of registers in the designed TTA processors freely, and recently > while experimenting with using TTA for a GPU design we have >

Hi, I wrote an LLVM blog post about our use of LLVM in the TCE project and a bit of a background for the TCE project in general. I hope some of you will find it interesting :) http://blog.llvm.org/2010/06/tce-project-co-design-of-application.html -- Pekka

TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). TTA is a minimalistic processor architecture template that allows high level of control for the designer to choose the boundary between the hardware and the software. The toolset provides a complete codesign flow from C programs down to

hi guys I need to get llvm to support vliw architecture. Can you please point me in the right direction. we have managed to get it to compile into simple assemble and now need it to be able to schedule the instructions in parrallel. any help would be appreciated Regards Junior

2010/6/29 Pekka Jääskeläinen <pekka.jaaskelainen at tut.fi>: > Hi, > > I wrote an LLVM blog post about our use of LLVM in the TCE project and a bit > of a background for the TCE project in general. I hope some of you will find > it interesting :) > > http://blog.llvm.org/2010/06/tce-project-co-design-of-application.html I'll ask here (rather than the TCE list)

On Jun 9, 2011, at 8:09 PM, David A. Greene wrote: > Note that things like instruction frequencies are highly ISA- > dependent. If possible, it is best to evaluate your ideas on more > than one target, just to see what the effects are. What other sorts > of things do you want to study? > > If, long-term, you are planning to do serious studies of performance >

Hi, Would it be possible to set tbgen to be installed with llvm? For our project http://llvm.org/ProjectsWithLLVM/#tta-tce it would be very helpful, because our tools generate compiler backend plugins in the fly for each customized processor and plugin generation needs tbgen for handling td files. Because of tbgen not beeing distributed, our users cannot use llvm from their favorite

Hi, On 08/09/2012 10:03 PM, Sergei Larin wrote: > I also tried to mess with PostRA scheduler to achieve similar goals, only > to find out that all the additional dependencies after RA make it virtually > impossible to produce high quality schedule, and obviously it is too late at > that point to address reg pressure via scheduling techniques, so I have put > that project on the

Here's the actual patch, sorry ;) On 12/07/2009 09:02 PM, Pekka Jääskeläinen wrote: > Hello, > > Can someone please commit this patch? > > Thanks. > > On 11/21/2009 11:15 PM, Pekka Jääskeläinen wrote: >> Hello, >> >> Attached is a trivial patch to increase the max number of physical >> registers in LLVM from 1024 to 16384. >> >> In

On May 4, 2009, at 11:03 PM, Mikael Lepistö wrote: > Hi, > > Would it be possible to set tbgen to be installed with llvm? For our > project http://llvm.org/ProjectsWithLLVM/#tta-tce it would be very > helpful, because our tools generate compiler backend plugins in the > fly for each customized processor and plugin generation needs tbgen > for handling td files. Sure,

Chris Lattner wrote: > > On May 4, 2009, at 11:03 PM, Mikael Lepistö wrote: > >> Hi, >> >> Would it be possible to set tbgen to be installed with llvm? For our >> project http://llvm.org/ProjectsWithLLVM/#tta-tce it would be very >> helpful, because our tools generate compiler backend plugins in the >> fly for each customized processor and plugin

Portable OpenCL (pocl) v0.6 released ------------------------------------ Portable OpenCL aims to be an efficient open source (MIT-licensed) implementation of the OpenCL 1.2 standard. In addition to producing an easily portable open source OpenCL implementation, another major goal of the project is improving performance portability of OpenCL programs with compiler optimizations, reducing the