similar to: [LLVMdev] LLVM-gcc for a new architecture

Boris, > How do I configure llvm-gcc (version 4.0.1) without having a gcc > back-end, but a LLVM back-end for my new architecture? This can be pretty tricky, because various target-related things are used in the frontend (consider e.g. ABI issues, alignment, etc). But in general you have just provide --target=<target triple> option to configure. I think it will fail, if target is

On Thu, Jun 20, 2013 at 6:14 AM, Boris Boesler <baembel at gmx.de> wrote: > Hi! > > I want to write a LLVM back-end for a bit addressing target architecture. > > http://llvm.org/docs/GetElementPtr.html#i-m-writing-a-backend-for-a-target-which-needs-custom-lowering-for-gep-how-do-i-do-thisstates quite clearly that some additional work must be done for this sort > of

Boris, > Yes, I know that. configure --target=a-b-c will fail because there > is no such stuff known in gcc. So, what is the answer/consequence? An > existing gcc back-end for architecture "a" is a precondition for a > LLVM back-end for architecture "a"? No. This is requirement of using gcc as a frontend. This looks pretty weird, but it is: frontend should

Hi! I want to write a LLVM back-end for a bit addressing target architecture. http://llvm.org/docs/GetElementPtr.html#i-m-writing-a-backend-for-a-target-which-needs-custom-lowering-for-gep-how-do-i-do-this states quite clearly that some additional work must be done for this sort of architecture. Is this still true? Is there a project/branch to make it more flexible? Support for any memory

Hi, I have written new dummy target to llvm-gcc for our processor architecture, which contains basically only the information which is necessary to generate llvm byte code. I could check tomorrow in work, which parts of llvm- gcc had to be altered for our "tce-llvm-gcc" cross-compiler. I also hardcoded compiler to use llvm-ld and llvm-as as it's bintools, for being able to

Hi! I'm making a strange observation in my backend, that ends in illegal code: Version 1: - I lower FrameIndex to TargetFrameIndex (nothing special) - I generate a special address-register ADD instruction in eliminateFrameIndex() to write FramePointer + offset into a new address-register - I use explicit load and store and address-registers in my target instruction patterns: eg (store

Hi! Am 05.11.2014 um 16:05 schrieb Tim Northover <t.p.northover at gmail.com>: > Hi Boris, > > On 5 November 2014 06:47, Boris Boesler <baembel at gmx.de> wrote: >> Cross-check: Move the MV-patterns from the beginning to the end. Voila, it works. > > It would be better to delete those patterns entirely. They'll always > match (if asked) and never give a

Hi Quentin, Am 01.11.2014 um 00:39 schrieb Quentin Colombet <qcolombet at apple.com>: > > On Oct 31, 2014, at 11:00 AM, Boris Boesler <baembel at gmx.de> wrote: > >> Hi Quentin, >> >> I added some debug output (N->dump()) in ::Select(SDNode*N) and compared it to the dot/Graphviz output (-view-legalize-types-dags; the last one with correct code). I

Hi Quentin, I added some debug output (N->dump()) in ::Select(SDNode*N) and compared it to the dot/Graphviz output (-view-legalize-types-dags; the last one with correct code). I found out, that some SDNodes are not passed to the ::Select(SDNode*N), approximately 11 nodes are missing. The first add-node (v1+v2) is missing. Is it normal that not all nodes are passes to ::Select()? Thanks,

Hi! I started writing a LLVM backend for a custom architecture. I have some register and instruction .td files and some other files/classes like a MCStreamer for assembler output. At the moment I can compile some empty programs so far. I implemented the method ::eliminateFrameIndex() similar to the Sparc and ARM backend. The method looks like this: // frame pointer is in reg of class

Hi Quentin, yes, this happens quite late. With the Option --debug-pass=Structure it's in or after "Assembly Printer". I do have a very simple DAGToDAGISel::Select() method: SDNode *MyTargetDAGToDAGISel::Select(SDNode *N) { SDLoc dl(N); // default implementation if (N -> isMachineOpcode()) { N -> setNodeId(-1); return NULL; // Already selected. } SDNode

Hi Quentin, Am 03.11.2014 um 23:30 schrieb Quentin Colombet <qcolombet at apple.com>: >> Continuing at 4309 >> Match failed at index 4310 >> Continuing at 4322 >> Morphed node: 0x7fef2a033610: i32 = MVrr 0x7fef2a033610 [ORD=21] >> >> >> Does the add operation become a MOVE instruction, or is this a chain of rules? > > Yes, your add becomes

The IR after LSR is: *** IR Dump After Loop Strength Reduction *** ; Preheader: entry: tail call void @fill_array(i32* getelementptr inbounds ([10 x i32], [10 x i32]* @buffer, i32 0, i32 0)) #2 br label %while.body ; Loop: while.body: ; preds = %while.body, %entry %lsr.iv = phi i32 [ %lsr.iv.next, %while.body ], [ 0, %entry ] %uglygep = getelementptr

Hi! During my backend development I get the error message for some tests: *** Bad machine code: Virtual register def doesn't dominate all uses. *** (C source-code, byte-code disassembly and printed machine code at the end of the email) The first USE of vreg4 in BB#1 has no previous DEF in BB#0 or #1. But why? I can't see how the LLVM byte-code is transformed to the lower machine code.

On Oct 19, 2007, at 8:15 AM, Boris Boesler wrote: > Hi! > > I'm writing a new back-end for a new architecture. First, I'll do > some "tests" with an existing back-end (I chose the Sparc back-end). > My architecture has special address-registers and I want to add such > new address-registers to my Sparc back-end. > > 1) I defined a new register call

Hi! >> I'm writing a new back-end for a new architecture. First, I'll do >> some "tests" with an existing back-end (I chose the Sparc back-end). >> My architecture has special address-registers and I want to add such >> new address-registers to my Sparc back-end. >> .... >> The GlobalAddress for variable c is replaced by an ADD(HI(c), LO

Hm, no. I expect byte addresses - everywhere. The compiler should not know that the arch needs word addresses. During lowering LOAD and STORE get explicit conversion operations for the memory address. Even if my arch was byte addressed the code would be false/illegal. Boris > Am 09.06.2020 um 19:36 schrieb Eli Friedman <efriedma at quicinc.com>: > > Blindly guessing here,

Hi Quentin, >> Yes, the dags in view-isel-dags and view-legalize-types-dags are correct (the add operations are here and are their results are used) and the dags are the same. > > And what about view-sched-dags? The DAG looks like I described below (*) > This one should give you what has been selected. So if this is not correct, you have indeed a problem in the selection

I'm targeting a machine that can only load and store aligned 64-bit words, but I'd like to be able to pack 8-, 16-, and 32-bit values into these words. Loads will require various shifts and masks; stores are more complicated. Does LLVM provide any support for such things? Is there an example target I can look at for ideas? Thanks, Preston -------------- next part -------------- An HTML

Hi! I'm writing a new back-end for a new architecture. First, I'll do some "tests" with an existing back-end (I chose the Sparc back-end). My architecture has special address-registers and I want to add such new address-registers to my Sparc back-end. 1) I defined a new register call AddrRegs 2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. )) 3) I