similar to: [LLVMdev] patch to docs/BitCodeFormat.html

Displaying 20 results from an estimated 400 matches similar to: "[LLVMdev] patch to docs/BitCodeFormat.html"

2013 Jan 09
2
[LLVMdev] Global variable initializer type does not match global variable type
Hello. I've managed to create a bitcode file (attached; also available at [1]) which produces a series of identical errors when verified: | Global variable initializer type does not match global variable type! | %i.NilClass* @nil When ran through llvm-dis and recompiled, through, it verifies successfully. If I disassemble it one more time, the result is identical to the first
2013 Jan 09
0
[LLVMdev] Global variable initializer type does not match global variable type
Peter Zotov писал 09.01.2013 19:59: > Hello. > > I've managed to create a bitcode file (attached; also available at > [1]) which produces > a series of identical errors when verified: > > | Global variable initializer type does not match global variable > type! > | %i.NilClass* @nil > > When ran through llvm-dis and recompiled, through, it verifies >
2016 Oct 13
4
Status of docs/BitCodeFormat.rst?
Hi folks, A while back I noticed some outdated information in docs/BitCodeFormat.rst about how parameter attributes were encoded — it describes an old encoding that was changed in 3.3 with the introduction of attribute groups. I opened a bug about this (https://llvm.org/bugs/show_bug.cgi?id=28941) and started trying to write a patch, but along the way ran into more and more issues (e.g. new
2016 Oct 13
2
Status of docs/BitCodeFormat.rst?
I think it just changed formats which prompted a change in ID -- the code now uses TYPE_BLOCK_ID_NEW (= 17). I haven’t looked deeply to see how different it is. Ismail > On Oct 13, 2016, at 2:02 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > >> On Oct 13, 2016, at 10:24 AM, Ismail Badawi (ibadawi) via llvm-dev <llvm-dev at lists.llvm.org> wrote: >>
2010 May 20
1
[LLVMdev] [PATCH] More BitCodeFormat.html improvements
The enclosed patch adds documentation for the PARAMATTR_BLOCK, TYPE_BLOCK, and TYPE_SYMTAB_BLOCK records in the LLVM IR bitcode format. I have started documenting CONSTANTS_BLOCK and FUNCTION_BLOCK and will send patches when they are complete. -Peter- -------------- next part -------------- An HTML attachment was scrubbed... URL:
2009 Oct 27
1
[LLVMdev] [PATCH] Improvements to BitCodeFormat.html
The enclosed patch contains a number of wording and clarity improvements to BitCodeFormat.html, and documents in detail the record types used within MODULE blocks. I plan to continue documenting the rest of the record types, but I wanted to submit patches in reasonably-sized pieces. -Peter S. Housel- housel at acm.org -------------- next part -------------- A non-text attachment was scrubbed...
2017 Apr 04
5
RFC: Adding a string table to the bitcode format
Hi, As part of PR27551 I want to add a string table to the bitcode format to allow global value and comdat names to be shared with the proposed symbol table (and, as side effects, allow comdat names to be shared with value names, make bitcode files more compressible and make bitcode easier to parse). The format of the string table would be a top-level block containing a blob containing
2017 Apr 04
4
RFC: Adding a string table to the bitcode format
On Mon, Apr 3, 2017 at 8:13 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On Apr 3, 2017, at 7:08 PM, Peter Collingbourne <peter at pcc.me.uk> wrote: > > Hi, > > As part of PR27551 I want to add a string table to the bitcode format to > allow global value and comdat names to be shared with the proposed symbol > table (and, as side effects, allow comdat
2017 Apr 04
4
RFC: Adding a string table to the bitcode format
On Mon, Apr 3, 2017 at 8:13 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On Apr 3, 2017, at 7:08 PM, Peter Collingbourne <peter at pcc.me.uk> wrote: > > Hi, > > As part of PR27551 I want to add a string table to the bitcode format to > allow global value and comdat names to be shared with the proposed symbol > table (and, as side effects, allow comdat
2011 Jan 24
3
[LLVMdev] How to change the type of an Instruction?
Hi, Nick, thanks for the reply. I still have a problem: I only need to "clone" an Instruction, changing its type. That is, I would like to keep all characteristics of the old Instruction and create a new one only with a different type. I am trying create a new Instruction thus: %3 = add nsw i32 %1, %2 ; <i16> [#uses=2] //Old Instruction Value* Op0 = I->getOperand(0); Value*
2010 Oct 02
1
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
Hi, >> DAGCombiner::visitBRCOND() has code: >> >> SDValue N1 = N->getOperand(1); >> SDValue N2 = N->getOperand(2); >> >> ... >> >> SDNode *Trunc = 0; >> if (N1.getOpcode() == ISD::TRUNCATE&& N1.hasOneUse()) { >> // Look past truncate. >> Trunc = N1.getNode(); >> N1 = N1.getOperand(0);
2017 Apr 04
2
RFC: Adding a string table to the bitcode format
On Tue, Apr 4, 2017 at 1:25 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On Apr 4, 2017, at 12:12 PM, Peter Collingbourne <peter at pcc.me.uk> wrote: > > On Mon, Apr 3, 2017 at 8:13 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > >> >> On Apr 3, 2017, at 7:08 PM, Peter Collingbourne <peter at pcc.me.uk> wrote: >> >> Hi,
2010 Sep 30
4
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
Bill Wendling wrote: > On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set
2019 Dec 31
3
Any significance for m_OneUse in (X / Y) / Z => X / (Y * Z) ??
Dear All, The InstCombine pass performs the following transformation. Z / (X / Y) => (Y * Z) / X This is performed only when operand Op1 ( (X/Y) in this case) has only one use in future. The code snippet is shown below. if (match(Op1, m_OneUse(m_FDiv(m_Value(X), m_Value(Y)))) && (!isa<Constant>(Y) || !isa<Constant>(Op0))) { // Z / (X / Y) => (Y *
2010 Sep 29
0
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > >> Our architecture has 1-bit boolean predicate registers. >> >> I've defined comparison >> >> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
2011 Jan 24
3
[LLVMdev] How to change the type of an Instruction?
On Mon, Jan 24, 2011 at 3:01 PM, Nick Lewycky <nicholas at mxc.ca> wrote: > On 01/24/2011 04:41 AM, Douglas do Couto Teixeira wrote: > >> Hi, >> >> Nick, thanks for the reply. >> I still have a problem: I only need to "clone" an Instruction, changing >> its type. That is, I would like to keep all characteristics of the old >> Instruction
2017 Sep 13
2
How to add optimizations to InstCombine correctly?
Hi, I am working on PR34474 and try to add a new optimization to InstCombine. Like in other parts of the visitMul function I add a Shl through the IR builder and create a new BinaryOp which I return from visitMul. If I understand correctly the new BinaryOp returned from visitMul should replace the original Instruction in the Worklist. However, I end up in an infinite loop and the Instruction
2010 Sep 29
1
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > Our architecture has 1-bit boolean predicate registers. > > I've defined comparison > > > def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; > > > > > But then I end up having the following bug: > >
2010 Oct 01
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > Bill Wendling wrote: >> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >> >>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>> >>>> Our architecture has 1-bit boolean predicate registers. >>>> >>>> I've defined comparison >>>> >>>> def
2015 Mar 09
2
[LLVMdev] LLVM Backend DAGToDAGISel INTRINSIC
I am currently working on DAGToDAGISel class for MIPS and am trying to figure out a way to use INTRINSIC_W_CHAIN for an intrinsic which can return a value. My intrinsic is defined as: Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrReadWriteArgMem]>; i.e. it has four arguments and one return value In DAGToDAGISel when I try to pass it with four arguments and