similar to: [LLVMdev] Predication before CodeGen

On Oct 7, 2007, at 12:51 AM, Nikhil A. Patil wrote: > Hi, > > I am planning to generate code for a peculiar architecture with > _no_ branch instructions (!), but with predicated loads and stores > to memory. This means the architecture is not Turing complete, is > going to waste a lot of computation, and any input program that can > hope to get compiled for this

On 08/10/2007, Evan Cheng <evan.cheng at apple.com> wrote: > > On Oct 7, 2007, at 12:51 AM, Nikhil A. Patil wrote: > > > Hi, > > > > I am planning to generate code for a peculiar architecture with > > _no_ branch instructions (!), but with predicated loads and stores > > to memory. This means the architecture is not Turing complete, is > > going

Hi all, I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we support or, and, and conditional predicates (see Scott Mahlke's papers on this

On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote: > Hi all, > > I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we

Hi Marcello, I am sure I've seen some postings on the list concerning architectures that support predicated execution and how to map that to LLVM IR, I'm just not sure anymore when and who was involved :). I have implemented your first suggestion for targets that do not have predicated instructions (where control flow to data flow conversion with explicit maintaining of masks and

On Fri, Oct 19, 2012 at 04:38:29PM +0100, Marcello Maggioni wrote: > Hello, > I'm working on a compiler based on LLVM for a SIMD architecture that > supports instruction predication. We would like to implement > branching on this architecture using predication. > As you know the LLVM-IR doesn't support instruction predication, so > I'm not exactly sure on what is the

Hi, I've done work on predicated SIMD representations for LLVM. If you search through the archives, you may find my "applymask" proposal, which is an attempt at representing predication in a very comprehensive way. I've since stopped pushing the proposal in part because Larrabee's changing fortunes led to a decline of interest at the time, in part because the proposal

We are currently doing something similar to your third option in Hexagon backend. But it is a VLIW so predication is not the only reason for that. Sergei --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Marcello

--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 On Thu, Jan 31, 2019 at 10:22 PM Jacob Lifshay <programmerjake at gmail.com> wrote: > > We're in-progress designing a RISC-V extension (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html) that would have variable-length vectors of short vectors (1 to 4): > <VL x <4 x

Philip Reames <listmail at philipreames.com> writes: >> Masking has advantages even in the default non-trapping fp >> environment: It is not uncommon for fp hardware to be slow on >> denormal values. If you take the operation + select approach, >> spurious computation on denomals could occur, slowing down the >> program. > Why?  If you're backend has

> The harm comes if the intrinsic ends up with the wrong value, or attached to the wrong loop. The intrinsic is marked as IntrNoDuplicate, so I wasn't worried about it ending up somewhere else. Also, it is a property of a specific loop, a tail-folded vector loop, that holds even after it is transformed I think. I.e. unrolling a vector loop is probably not what you want, but even if you do

I am looking for feedback to add support for a new loop pragma to Clang/LLVM. With "#pragma tail_predicate" the idea would be to indicate that a loop epilogue/tail can, or should be, folded into the main loop. I see two use cases for this pragma. First, this could be interesting for the vectorizer. It currently supports tail folding by masking all loop instructions/blocks, but does this

Hello, I'm working on a compiler based on LLVM for a SIMD architecture that supports instruction predication. We would like to implement branching on this architecture using predication. As you know the LLVM-IR doesn't support instruction predication, so I'm not exactly sure on what is the best way to implement it. We came up with some ways to do it in LLVM: - Do not add any

Hi Roger, That's a good example, that shows most of the moving parts involved here. In a nutshell, the difference is, and what we would like to make explicit, is the vector trip versus the scalar loop trip count. In your IR example, the loads/stores are predicated on a mask that is calculated from a splat induction variable, which is compared with the vector trip count. Illustrated with your

Ralf Karrenberg <Chareos at gmx.de> writes: > I am sure I've seen some postings on the list concerning architectures > that support predicated execution and how to map that to LLVM IR, I'm > just not sure anymore when and who was involved :). I was one of them. I suggested adding general predication to the LLVM IR but that doesn't look like it's going to happen.

Dan Gohman <dan433584 at gmail.com> writes: > And, in part because a popular trend seems to be to have SIMD units > which don't trap or raise exception flags on arithmetic and which don't > go faster when predicated, such that there's no  reason to predicate > anything except stores and occasionally loads. On these architectures, > simply having intrinsics for

Hi, I was wondering if LLVM supports predicates and conditional execution. Something like we have in IA64. There is a register class of predicates and then every instruction may be predicated by a register from this class. For example: cmp_less p, x, y // p is a predicate which gets the result of x < y p add x, x, 2 // if p then do the add instruction Is there support in LLVM to something

hi, we're trying to come up with a static compiler based on llvm for a 4- way vliw architecture with full support for predicated execution. a distinguishing feature is the omission of flag registers. instead, conditions can be paired with a particular instruction within the same bundle. a performance critical issue will be proper use of predicated execution. if-conversion can either

Hi, There is now an RFC for a roadmap to native vector predication support in LLVM and a prototype implementation:   https://reviews.llvm.org/D57504 The prototype demonstrates: -  Predicated vector intrinsics with an explicit mask and vector length parameter on IR level. -  First-class predicated SDNodes on ISel level. Mask and vector length are value operands. -  An incremental strategy

Why is this a regalloc problem? I assume in the example below the "r0" is somehow forced by the ABI? Because otherwise moving the texture2d operation into the branch wouldn't matter as long as we assign different registers to the two branches and use a technique like lib/Target/R600/SIFixSGPRLiveRanges.cpp. - Matthias > On May 13, 2015, at 6:00 PM, Philip Reames <listmail at