similar to: [LLVMdev] Instruction selector internals

Hi Evan > > It looks > > like that the instruction selector operates on actual DAGs, no > > unDAGing to > > trees seems to occur at any point. > Instruction scheduler is responsible for turning a DAG into a list of > instructions. So unDAGing is applied by the instruction scheduler. At which points in the compilation flow is the instruction scheduler run (i'm

Hi there first of all, many thanks to some people out there for their advice on building LLVM on Cygwin (this would be Aaron Gray, Reid Spencer, Tanya and Chris Lattner i suppose). LLVM 2.1 seems to build in debug mode on my "old" Cygwin (1.5.15). At least everything except tblgen is build. For tblgen i use the supplied mingw binaries, many thanks for that! I would like now to ask you

Hi there, I have a question on the LLVM internals. Is it possible to dump an InstructionList (i.e. a (possibly) naively scheduled assembly) prior register allocation? Does LLVM use infinite (virtual) registers similar to MachSUIF? This is, of course, meant for a given target in contrast to MachSUIF that features the SUIFvm ISA as low-level IR and such a dump is possible at this point. Plus:

Hi Nikolaos, Following commands work great for me. $ clang -S -emit-llvm -target nvptx -x cl -include clc/clctypes.h ../data-types/scalar.cl $ llc -mcpu=sm_30 scalar.s You can follow Justin's blog [1]. It helped me a lot to understand where to start. [1] http://jholewinski.org/blog/llvm-3-0-ptx-backend/ Best, Ankur On Mon, Feb 4, 2013 at 11:40 PM, Justin Holewinski < justin.holewinski

Hi Duncan >>> br i1 %38, label %17, label %39 >>> ; <label>:39 ; preds = %._crit_edge >>> ret void >>> >>> However, ";" is a comment-line character. How is this interpreted, as a >>> meta-comment? (a semantically important comment)? >> >> it's just a comment and has no

Hi there i would like to ask a few questions to the developers responsible for the register allocator(s) design in LLVM (Fernando and other people). First of all, congrats on providing more than one option for register allocation. Now to the questions: 1. I can see the standard algorithms (bigblock, linearscan -- good choice for the JIT and for general use as well, and the other algorithms).

Alright, couple of points here: 1. Address space 0 is invalid for global variables. This is causing a crash in llc where we use llvm_unreachable() on this case. This is most likely why you're seeing llc run forever. The fix for this is to use address space 1 for globals, which puts them into PTX global memory. On our side, we should provide a meaningful error message in this case. 2. The

Hi, > Can you post the llc command line you're using? Can you post an LLVM IR > file that causes this behavior? yes: ${LLVM_PATH}/bin/llc -o helloworld.s -march=nvptx helloworld.ll where LLVM_PATH my local installation path for LLVM. Also attaching helloworld.c: #include <stdio.h> int main(void) { printf("Hello World!\n"); return 0; } and helloworld.ll:

On Mon, Feb 4, 2013 at 1:09 PM, <nkavv at physics.auth.gr> wrote: > Hi Justin, > > > Has anyone had similar problems with the NVPTX backend? Shouldn't this >>> code be linked to the AsmPrinter library for NVPTX (already)? >>> >> >> What do you mean by "doesn't work"? The AsmPrinter library really houses >> the MCInst

> > 1. I can see the standard algorithms (bigblock, linearscan -- good > > choice for > > the JIT and for general use as well, and the other algorithms). Is > > it possible > > to pre-allocate registers in your linearscan (or in another > > allocation engine) > > for specific source-level or (better) intermediate code (bitcode) > > level > >

Hi Duncan >> br i1 %38, label %17, label %39 >> ; <label>:39 ; preds = %._crit_edge >> ret void >> >> However, ";" is a comment-line character. How is this interpreted, as a >> meta-comment? (a semantically important comment)? > > it's just a comment and has no semantic comment. You can delete

Hi Justin, >> Has anyone had similar problems with the NVPTX backend? Shouldn't this >> code be linked to the AsmPrinter library for NVPTX (already)? > > What do you mean by "doesn't work"? The AsmPrinter library really houses > the MCInst printer, which isn't implemented for NVPTX yet. The older > assembly printer works just fine. This is

Hi Nikolaos, On 20/01/13 12:00, nkavv at physics.auth.gr wrote: > Hi all, > > i'm writing a TXL (http://www.txl.ca) grammar and a revamp of bison/flex grammar > for LLVM. > > I've noticed an inconsistency regarding label naming conventions. > > For instance, the following is a segment of legit LLVM assembly (human-readable) > IR: > > br i1 %38, label

> From: Mikael Lepist? <mikael.lepisto at tut.fi> > > Hi, Hi Mikael > I was talking with aKor in #llvm how we could implement custom operation > support for our ASIP architecture. We came into solution that the best > way would be to write new custom operation intrinsic and optimization > pass for raising certain type of function calls to those intrinsics > (similar

Hi all, i'm writing a TXL (http://www.txl.ca) grammar and a revamp of bison/flex grammar for LLVM. I've noticed an inconsistency regarding label naming conventions. For instance, the following is a segment of legit LLVM assembly (human-readable) IR: br i1 %38, label %17, label %39 ; <label>:39 ; preds = %._crit_edge ret void

On Thu, Jan 24, 2013 at 7:20 AM, Ahmed Bougacha <ahmed.bougacha at gmail.com>wrote: > On Thu, Jan 24, 2013 at 12:46 PM, <nkavv at physics.auth.gr> wrote: > > Hi all, > > > > i'm just starting out with LLVM (although i've been observing its > evolution > > since that first release some years ago :) > > > > I would like to develop a

On Thu, Jan 24, 2013 at 12:46 PM, <nkavv at physics.auth.gr> wrote: > Hi all, > > i'm just starting out with LLVM (although i've been observing its evolution > since that first release some years ago :) > > I would like to develop a backend for a generic assembly-like language, > called NAC (N-Address Code). More info on NAC can be found here: >

> From: "Wilfred L. Guerin" <wilfredguerin at gmail.com> > Subject: [LLVMdev] LLVM Expansions > > It is very relevant that LLVM look into handeling HDL and other binary > and analogue operation modeling capbilities, as well as expand this what is binary? you mean digital right? > Without confirming the true characteristics of the lower structure > types and

On Oct 6, 2007, at 6:11 PM, nkavv at physics.auth.gr wrote: >>> You mean a temporary defined in an instruction. OK, that is what i >>> basically >>> need here. Is it guaranteed to "live" in the physical register for >>> the entire >>> program (or at least for a single function, which would trivially >>> work for >>>

> > You are thinking about the gcc extension which allows the programer > to tie a register to global variable? This feature isn't implemented > nor am I aware of anyone driving to get it to implemented. Looks like > you will have to roll up your sleeves if that's what you want. :-) > > Evan Hi Evan is this the -fixed-reg<num> feature, or something that has