similar to: [LLVMdev] Profiling llc

Hi, Standard approach to profiling dynamically loaded libraries with gprof doesn't seem to work with LLVM: export LD_PROFILE=Mylib.so export LD_PROFILE_OUTPUT=. make ENABLE_PROFILING=1 // compiling my project opt -load Profile/Mylib.so -options... but no Mylib.so.profile (or gmon.out) is produced. Profiling libc.so.6 usage by "ls -l", however, works fine. Could anyone explain

Howdy. I'm working on Altivec versions of some of the libFLAC functions. I figured the best candidates would be those that had MMX/SSE/3dnow versions, and I picked FLAC__lpc_restore_signal() to do first, since it's relatively simple. In stepping through some runs, it appears that 'order' mod 4 is always 0. Is that guaranteed, either by the format or by higher functions in the

Hi, I am trying to obtain basic block profiles for mediabench g721 benchmark. I have successfully built llvm in profile_enabling mode. Then so as to find out the block execution frequency, I ran the command, analyze encode.out-cbe. It generated gmon.out which I read using gprof. However, I did not get the basic block level execution frequency. Can anybody help me as to how I can extract the basic

Does anyone have any advice about profiling C/C++ code in a package under R? Does R need to be built specially for this to work? The FAQ has some entries about profiling but they cover R level profiling; I'm try to get at the C++ code I've written that is called from R. Primary target is Mac OS X. Thanks. Ross Boylan

On 11/23/07, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > Hi, Sanjiv, > > those passes operate on the whole machine function. Each machine > function contains many basic blocks. If a program has many functions, the > register allocator will be called as many times, i.e it does not do > interprocedural allocation. > > best, > >

Dear guys, I want to coalesce some copies, and I would like to know if there is any method that I can call, like JoinCopy from the old (LLVM 1.9) LiveIntervals class. I found it in SimpleRegisterCoalescing (LLVM 2.1), but I do not want to call this analysis, as I have my own. basically, I can determine that two virtuals do not overlap, and I know that it is safe to join them. In

Hi Florian, we though about using UIUC, like in LLVM. Do you guys know if that could be a problem, given that we are mining the functions from github? > Have you thought about integrating the benchmarks as external tests into LLVM’s test-suite? That would make it very easy to play around with. We did not think about it actually. But we would be happy to do it, if the community accepts

Hello, I have a problem with Hausman test. I am performing my analysis with these commands: > library(plm) > data<-read.csv2("paolo.csv",header=TRUE) > data< pdata.frame(data,index=c("FIRM","YEAR"),drop.index=TRUE,row.names=TRUE) > RECEIV~LSIZE+LAGE+LAGE2+CFLOW+STLEV+FCOST+PGROWTH+NGROWTH+TURN+GPROF+GPROF2 >

Note the typo in your 3rd line: data < Don't know if this means anything... Bert On Feb 11, 2018 7:33 AM, "PAOLO PILI" <paolo.pili at student.unife.it> wrote: > Hello, > > I have a problem with Hausman test. I am performing my analysis with these > commands: > > > library(plm) > > data<-read.csv2("paolo.csv",header=TRUE) >

Thanks again. One more question here: Since the regalloc works once per function, do I stil have access to the Call graph? Just saving information between regalloc passes for different functions may not be enough for my case. I will need to maintain the regalloc info of various passes in the call graph order. Anyways thanks for your inputs. I will get back if I need to learn more. Sanjiv On Nov

Hi, again, I think you can do it in the same way that the other allocators have been coded, i.e extend RA, register the pass and so forth. I am not sure about the best way to pass information among a run of RegAlloc to the other, maybe the other guys in the list could suggest something. Yet, you can always dump it into a file, and read it again, everytime it is necessary. Remember that

Dear LLVMers, I need help with one error in my register allocator. I am getting errors when folding instructions for the x86 (it does not happen when I use the PowerPC as target). The problem is that, when I execute something like: mi = mbb->insert(mbb->erase(mi), fmi), where mbb is a MachineBasicBlock, valgrind gives this error message: Address 0x42C62B0 is 24 bytes inside a block

Hey, guys, I am creating some move instructions with MRegisterInfo::copyRegToReg. How do I get a pointer to the instruction that I just created? Is there a way to do something like: // mbb is MachineBasicBlock, reg_info is MRegisterInfo MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); reg_info->copyRegToReg(mbb, iter, dst, src, rc); iter--; (???) MachineInstr *

>> And I have a quite fast algo that I believe is simpler than [Budimlic02] >> and I can share it with you :) > > Do you have a paper on this? I'd be interested in seeing it. > Yes, I have a tech report on this page: http://compilers/fernando/projects/soc/ and I have submitted a paper to SAS, and now I am waiting for the review. The coalescing algorithm is described in

Dear guys, what is the best way to implement a swap of floating point registers in X86? For the integer registers, I am using xchg. Is there a similar instruction for floating point? My function to insert swaps is like: void X86RegisterInfo::swapRegs( MachineBasicBlock & mbb, MachineBasicBlock::iterator mi, unsigned r1, unsigned r2, const TargetRegisterClass

Guys, I am in need of a no-op instruction: an instruction that does not do anything, and has no operands. Does LLVM predefine such an instruction? I want to transform the program so that there is no empty basic block. Fernando

Hi, guys, What is the opcode of the instruction to swap two registers in X86? After updating my LLVM branch, I realized that there is no longer an opcode for xchg with two register operands in X86GenInstrNames.inc. I found only instructions to swap memory and registers: XCHG16rm, XCHG32rm, XCHG64rm and XCHG8rm. I am updating from LLVM 2.1 to current trunk. The names that I was

you are right about the 3rd line but it doesn't help me for my problem. I remove the 3rd line but there is still the same problem: Error in solve.default (dvcov): the system is numerically unique: reciprocity condition value = 1.63418e-19 Paolo 2018-02-11 16:54 GMT+01:00 Bert Gunter <bgunter.4567 at gmail.com>: > Note the typo in your 3rd line: data < > > Don't

Dear llvmers, I am trying to insert a move instruction where both source and destination registers are physical registers. How is the code for this? I tried this one here: void PhiDeconstruction_Fer::add_move ( MachineFunction & mf, MachineBasicBlock & mbb, unsigned

> And I have a quite fast algo that I believe is simpler than [Budimlic02] > and I can share it with you :) Do you have a paper on this? I'd be interested in seeing it. -Tanya > > Fernando > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >