similar to: [LLVMdev] Dynamically alternating between register allocators

Hi Fernando, To do this you would need to change the register allocation pass on the fly. I don't think this is currently possible. Someone please correct me if I am wrong. I would like to see hierarchical pass capability built into pass manager. This allows us to group live variables, phi lowering, two- address, lower subreg, live interval analysis, coalescing, allocation, and

This doesn't necessarily need to be in the passmanager, but I'd like to see the code generator grow the ability to codegen an entire function multiple times. Ideally, we'd be able to codegen all the way to final machineinstrs in multiple configurations and then pick the best based on some metric. This would allow lots of interesting experiments and allow people willing to

Dear Anton, you can add your register allocator strait iin the "lib/CodeGen/Passes.cpp", and then 're-make' it: "makellvm llc", on the top of lib/CodeGen. It is faster than running make from LLVMOBJDIR. The problem is that it only add to llc the changes on the lib/CodeGen directory. If you change other parts, a make from LLVMOBJDIR will synchronize it. Try adding

The short answer is this is not currently done. LLVM register allocator does not currently use a move to a different register class in lieu of spills. This is definitely something we should do in the future. Can you file a bugzilla enhancement request? Thanks, Evan On Jun 13, 2007, at 11:09 AM, Chris Lattner wrote: > On Tue, 12 Jun 2007, Fernando Magno Quintao Pereira wrote: >>

On 11/23/07, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > Hi, Sanjiv, > > those passes operate on the whole machine function. Each machine > function contains many basic blocks. If a program has many functions, the > register allocator will be called as many times, i.e it does not do > interprocedural allocation. > > best, > >

Does this depend on vreg subreg support? It sounds as if it could be vaguely related, but I'm not sure it's necessary. -- Chris On Jun 14, 2007, at 12:27 PM, Evan Cheng wrote: > The short answer is this is not currently done. LLVM register > allocator does not currently use a move to a different register class > in lieu of spills. This is definitely something we should do in

Hi, again, I think you can do it in the same way that the other allocators have been coded, i.e extend RA, register the pass and so forth. I am not sure about the best way to pass information among a run of RegAlloc to the other, maybe the other guys in the list could suggest something. Yet, you can always dump it into a file, and read it again, everytime it is necessary. Remember that

Thanks again. One more question here: Since the regalloc works once per function, do I stil have access to the Call graph? Just saving information between regalloc passes for different functions may not be enough for my case. I will need to maintain the regalloc info of various passes in the call graph order. Anyways thanks for your inputs. I will get back if I need to learn more. Sanjiv On Nov

Dear llvmers, I am trying to insert a move instruction where both source and destination registers are physical registers. How is the code for this? I tried this one here: void PhiDeconstruction_Fer::add_move ( MachineFunction & mf, MachineBasicBlock & mbb, unsigned

Dear guys, I want to coalesce some copies, and I would like to know if there is any method that I can call, like JoinCopy from the old (LLVM 1.9) LiveIntervals class. I found it in SimpleRegisterCoalescing (LLVM 2.1), but I do not want to call this analysis, as I have my own. basically, I can determine that two virtuals do not overlap, and I know that it is safe to join them. In

>> And I have a quite fast algo that I believe is simpler than [Budimlic02] >> and I can share it with you :) > > Do you have a paper on this? I'd be interested in seeing it. > Yes, I have a tech report on this page: http://compilers/fernando/projects/soc/ and I have submitted a paper to SAS, and now I am waiting for the review. The coalescing algorithm is described in

Hi Florian, we though about using UIUC, like in LLVM. Do you guys know if that could be a problem, given that we are mining the functions from github? > Have you thought about integrating the benchmarks as external tests into LLVM’s test-suite? That would make it very easy to play around with. We did not think about it actually. But we would be happy to do it, if the community accepts

Dear LLVMers, I wish someone could help me to clarify a register allocation question. I will use X86 in this example, but it really does not matter too much. Imagine that I have a virtual v stored in register AL, and I am about to cross a function call, that effectively overwrites AL. Well, I have, say, register ESI free, but as it happens, ESI is bigger than AL. It should be

> And I have a quite fast algo that I believe is simpler than [Budimlic02] > and I can share it with you :) Do you have a paper on this? I'd be interested in seeing it. -Tanya > > Fernando > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >

Hi guys, I have been using a debugger for my register allocator. The debugger happened to be very useful at catching register assignment errors. I've put the debugger on-line, if anyone who is working with register allocation wants to use. The debugger itself has nothing to do with LLVM, but I've coded a spiller that prints the code in a format that the debugger can read. The

Hey, guys, I am creating some move instructions with MRegisterInfo::copyRegToReg. How do I get a pointer to the instruction that I just created? Is there a way to do something like: // mbb is MachineBasicBlock, reg_info is MRegisterInfo MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); reg_info->copyRegToReg(mbb, iter, dst, src, rc); iter--; (???) MachineInstr *

Guys, I am in need of a no-op instruction: an instruction that does not do anything, and has no operands. Does LLVM predefine such an instruction? I want to transform the program so that there is no empty basic block. Fernando

Dear guys, what is the best way to implement a swap of floating point registers in X86? For the integer registers, I am using xchg. Is there a similar instruction for floating point? My function to insert swaps is like: void X86RegisterInfo::swapRegs( MachineBasicBlock & mbb, MachineBasicBlock::iterator mi, unsigned r1, unsigned r2, const TargetRegisterClass

Guys, I need advice in how to handle a problem. The problem: In X86_64, pointers are 64-bit variables, and are stored into 64-bit registers. However, some pointers are small enough that they can be represented as 32-bit values. Is there some way, in LLVM, to recognize which pointers can be stored into 32-bit registers, and so modify their class accordingly? Any ideas or hints would

On Thu, 12 Apr 2007, Fernando Magno Quintao Pereira wrote: >> I'm definitely interested in improving coalescing and it sounds like >> this would fall under that work. Do you have references to papers >> that talk about the various algorithms? > > Some suggestions: > > @InProceedings{Budimlic02, > AUTHOR = {Zoran Budimlic and Keith D. Cooper and Timothy