similar to: [LLVMdev] How to put a pass for last?

Hi all, A week agoo I sent an email about reordering instruction in basicblocks. And ... I was able to do it. I guess so, at least. Now when compiling my test program, llc dumps: -- llc: /home/mentat/llvm_work/llvm/lib/CodeGen/LiveVariables.cpp:155: void llvm::LiveVariables::HandleVirtRegUse(llvm::LiveVariables::VarInfo&, llvm::MachineBasicBlock*, llvm::MachineInstr*): Assertion

Hello, I am new here. This is my first post. I spent about three days on trying out LLVM by developing a front-end which is able to generate LLVM IR for a subset of C language. I have not applied any optimization pass yet. On linux, it can go all the way through with the system native assemlber and linker to generate executables. And it runs. I ran into problems on Windows since the generated

Yup, You are right. That exploded. I missed some lines in between. there was a .reserve(total) in the actual code. But, there is some side effect I still could not find. 2007/8/16, Chris Lattner <sabre at nondot.org>: > > On Wed, 15 Aug 2007, [ISO-8859-1] Emílio Wuerges wrote: > > -- > > int total = BB->size(); > > std::vector<MachineInstr*>

For adding the nop: TII->insertNoop(*BB, BB->end()); 2007/8/9, Chris Lattner <sabre at nondot.org>: > > On Thu, 9 Aug 2007, [ISO-8859-1] Emílio Wuerges wrote: > > I too believe it should not be complicated. > > But I was not being able to do it. > > Finally, after some thinking (and tinkering), this worked like a charm: > > > > MachineInstr* mi =

Is this thread suposed to be a bad joke? 2008/5/10 kr512 <kr512 at optusnet.com.au>: > > Chris Lattner wrote: >> If you'd prefer to use GCC, go for it. No one is forcing >> you to use LLVM. > > No, we would prefer to use LLVM, but a missing part in LLVM > makes it difficult. It would be wonderful if this missing > part could be supplied. > >> You

Hi Tanya and everybody, Ty for your support. I too believe it should not be complicated. But I was not being able to do it. For instance, I tried to run this code below: BB->push_back(&(BB->front())); BB->pop_front(); But it did not work (kinda obvious why). Nor this: BB->push_back(BB->begin()); BB->pop_front(); But also did not work. It seams the same

Hi, There are some generated Sparc assembly code like this: main: ! @main ! BB#0: save %sp, -112, %sp sethi 0, %l0 or %g0, 5, %l1 st %l0, [%fp+-4] st %l1, [%fp+-8] st %l1, [%fp+-12] sethi %hi(.L.str), %l1 ld [%fp+-8], %o1 add %l1, %lo(.L.str), %l1 or %g0, %l1, %o0 call printf nop ld [%fp+-12], %o2 ld [%fp+-8], %l2 sethi %hi(.L.strQ521), %l3 add

On Wed, 15 Aug 2007, [ISO-8859-1] Em�lio Wuerges wrote: > -- > int total = BB->size(); > std::vector<MachineInstr*> positionmap(total); > for (int i = 0; i< total; ++i) > positionmap.push_back(BB->remove(BB->begin())); > for(int i = 0; i< total; ++i) > BB->push_back(positionmap[i]); > -- This doesn't do what you think. This line:

On May 10, 2008, at 8:41 PM, Emílio Wuerges wrote: > Is this thread suposed to be a bad joke? I thought jokes were funny? ;-) -Chris

Ok, as I said, the most precise way to figure out what's wrong is to emit LLVM IR first (use clang -emit-llvm ...) and check out how it differs from working examples, for instance, nvptx regression tests. ----- Original message ----- > I'm building this with llvm-c, and accessing these intrinsics via calling > the intrinsic as if it were a function. > > class F_SREG<string

Hi Timothy, I'm not sure what you mean by this working for other intrinsics, but in this case, I think you want the intrinsic name llvm.nvvm.read.ptx.sreg.tid.x. For me, this looks like: %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() Pete On Fri, Mar 1, 2013 at 11:51 AM, Timothy Baldridge <tbaldridge at gmail.com> wrote: > I'm building this with llvm-c, and accessing these

The identifier INT_PTX_SREG_TID_X is the name of an instruction as the back-end sees it, and has very little to do with the name you should use in your IR. Your best bet is to look at the include/llvm/IR/IntrinsicsNVVM.td file and see the definitions for each intrinsic. Then, the name mapping is just: int_foo_bar -> llvm.foo.bar() int_ prefix becomes llvm., and all underscores turn into

GCC for AVR is awesome but, as far as I know, until very little time ago, compiler support for PIC was close to none. 2008/5/19 Jonathan S. Shapiro <shap at eros-os.com>: > I have a client who might well make use of an AVR32 port, but I suspect > that machine is very different than the one you are currently examining. > > > shap > On Mon, 2008-05-19 at 12:38 -0600, John

Hello guys, I plan to do some pre register allocation optimizations. I already know my way around LLVM but I could use some more experience. I need a way to reorder instructions inside MachineBasicBlocks or MachineFunctions. I've been searching for it but I have not found an example in the code yet. Can someone point me where I should look for? ty, -- Emilio Wuerges LAPS - Laboratorio

On Thu, 9 Aug 2007, [ISO-8859-1] Em�lio Wuerges wrote: > I too believe it should not be complicated. > But I was not being able to do it. > Finally, after some thinking (and tinkering), this worked like a charm: > > MachineInstr* mi = BB->remove(BB->begin()); > BB->push_back(mi); > > But, is there a better way to do it? This is a good way to do a single

I'm building this with llvm-c, and accessing these intrinsics via calling the intrinsic as if it were a function. class F_SREG<string OpStr, NVPTXRegClass regclassOut, Intrinsic IntOp> : NVPTXInst<(outs regclassOut:$dst), (ins), OpStr, [(set regclassOut:$dst, (IntOp))]>; def INT_PTX_SREG_TID_X : F_SREG<"mov.u32 \t$dst, %tid.x;",

I've written a compiler that outputs PTX code, the result seems fairly reasonable, but I'm not sure the intrinsics are getting compiled correctly. In addition, when I try load the module using CUDA, I get an error: CUDA_ERROR_NO_BINARY_FOR_GPU. I'm running this on a 2012 MBP with a 640M GPU. PTX Code (for a mandelbrot calculation): // // Generated by LLVM NVPTX Back-End //

Timothy, Those calls to compute grid intrinsics are definitely wrong. In ptx code they should end up into reading special registers, rather than function calls. Try to take some working example and figure out the LLVM IR differences between it and the result of your compiler. - D. ----- Original message ----- > I've written a compiler that outputs PTX code, the result seems fairly >

On 11/12/2009, at 10:43 AM, Anton Korobeynikov wrote: > Hi, Chris > >> That is target independent code, so you should not put sparc specific changes there. It sounds like one of the sparc-specific target hooks is wrong. > Since sparc does not provide any hooks for operation of branches (e.g. > AnalyzeBranch and friends) it might be possible that generic codegen > code is

Hi, I'm installing CentOS5 on a HP DL380-G4 server with 4Gb RAM. It had SLES9 on it, and SLES9 find all the RAM. But now CentOS5 x86_64 can't find all the RAM. From free: [root at Suzuka ~]# free total used free shared buffers cached Mem: 3986376 1591996 2394380 0 113896 1180852 -/+ buffers/cache: 297248