similar to: [LLVMdev] inline assembly

Hi, Apologies this is a bit lengthy. TLDR: I'm using Dragonegg + LLVM 3.2 and uClibc, and am finding that using the Fast register allocator (i.e. -optimize-regalloc=0) causes miscompilation of setsockopt calls (5-arg system calls). The problem doesn't happen with the default register allocation path selected. It can be worked around by manually simplifying the system call setup

Hi, I’m facing a crash issue (--target=arm-linux-gnueabi -march=armv8-a+crc -mfloat-abi=hard) and debugging the problem, I found that an intended branch was not taken due to bad code generation after the Post RA Scheduler pass. A CMPri instruction after an INLINEASM block (which inturn contains a cmp, bne instruction) is being moved before the INLINEASM block incorrectly resulting in two

Consider this program: --- asm.c --- int G; int foo(char *p) { int rv; G = 0; asm ("" : "=r"(rv) : "r"(p) : "memory"); return rv + G; } ------------- Is the use of "memory" clobber sufficient to expect the optimizer not to optimize the "+ G" away in the return statement? I'll add here that

switching to newer linux-libc-dev linux-2.6 provided kernel headers worked fine beside on mips mipsel: In file included from usr/klibc/arch/mips/crt0.S:11: usr/include/arch/mips/machine/asm.h:8:24: error: asm/regdef.h: No such file or directory usr/include/arch/mips/machine/asm.h:9:21: error: asm/asm.h: No such file or directory i'm not sure if you want to export both headers in

Hi, On SystemZ there are a set of "access registers" that can be copied in and out of 32-bit GPRs with special instructions. These instructions can only perform the copy using low 32-bit parts of the 64-bit GPRs. As reported and discussed at https://bugs.llvm.org/show_bug.cgi?id=44254, this is currently broken due to the fact that the default register class for 32-bit integers is

Hi llvm-dev, I am currently writing a backend for an architecture I am designing in my bachelor's thesis and recently came across the GlobalISel Selection Framework. Should already start using this over the more common Selection DAG? Being new llvm backend development, I am not sure if GlobalISel would be "easier" to implement than ISelDAG and if there is any decent documentation on

On 10 May 2014, at 18:14, Tim Northover <t.p.northover at gmail.com> wrote: >> The easiest solution would be to extend the cmpxchg instruction with a >> weak variant. It is then trivial to map load, modify, weak-cmpxchg to >> load-linked, modify, store-conditional (that is what weak cmpxchg was >> intended for in the C[++]11 memory model). > > That would

The parts of klibc specific to the mips architecture. Signed-off-by: H. Peter Anvin <hpa at zytor.com> --- commit 8dc79563c06020d8844b9e9b821741828039b59e tree b957c8fb1fddf486f5c26b1880726051d4f6aaad parent bc9b363b31d301ab94c115cccc2e079c0d318498 author H. Peter Anvin <hpa at zytor.com> Sun, 25 Jun 2006 16:58:31 -0700 committer H. Peter Anvin <hpa at zytor.com> Sun, 25 Jun

2013/6/23 David Chisnall <David.Chisnall at cl.cam.ac.uk> > Hi, > > In our version of LLVM, we've added different-sized iPTR* types, so we > have an iPTR256 for our fat pointers. This causes some problems with > constraints, because the way that TableGen resolves constraints is not > expected to handle multiple pointer types. We've added a flag that can be >

Hi, I write again regarding buildSchedGraph(), as I am still not happy about things there. I have found at least two examples which do not work out: 1) SU(2) Store "Value A" SU(1) Store "Value A" SU(0) Load "Value A" If MIsNeedChainEdge() returns false for SU(0) and SU(1), SU(0) is inserted into RejectedMemNodes and removed from its MemUses SU list, as this

Hi, I'm not sure. But in your lowered DAG the chain nodes are the first operands for you custom nodes, however for the other nodes the chain is the last operand. I seem to remember that during targetlowering the chain is the first operand and then it seems to switch over after ISelDAG, this confused me and may have something to do with the issue that you are seeing. I really don't

Hi all, I noticed that the x86 backend tends to emit unnecessary vector insert instructions immediately after sse scalar fp instructions like addss/mulss. For example: ///////////////////////////////// __m128 foo(__m128 A, __m128 B) { _mm_add_ss(A, B); } ///////////////////////////////// produces the sequence: addss %xmm0, %xmm1 movss %xmm1, %xmm0 which could be easily optimized into

> On Jul 3, 2019, at 4:43 PM, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > -----Original Message----- > From: David Greene <dag at cray.com> > Sent: Wednesday, July 3, 2019 2:44 PM > To: Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> > Cc: Krzysztof Parzyszek <kparzysz at quicinc.com> > Subject: [EXT] Re:

On 10 May 2014, at 16:18, Tim Northover <t.p.northover at gmail.com> wrote: > Actually, I really agree there. I considered it recently, but decided > to leave it as an intrinsic for now (the new IR expansion pass happens > after most optimisations so there wouldn't be much benefit, but if we > did it earlier and the mid-end understood what an ldrex/strex meant, I > could

Guys, I've heard about some absurd RAM requirements for 9.1, has anybody tested it? e.g. http://forums.freebsd.org/showthread.php?t=36314 -- View this message in context: http://freebsd.1045724.n5.nabble.com/9-1-minimal-ram-requirements-tp5771583.html Sent from the freebsd-stable mailing list archive at Nabble.com.

Hi, I have revisited the issue in buildSchedGraph() I talked about previously, and attached a few patches. The first tries to fix the issue, and the other two try to illustrate associated issues, emerged from applying it. Is it OK to commit the first patch? [PATCH] Bugfix for missed dependency from store to load in buildSchedGraph(). Bugfix for missed dependency from store to load in

Hi, > 1 What side effects do operatios of loads/stores/calls/returns have? > (maybe i don't understand concept of side effect ) suppose you do a store to a memory location, and then load from the memory location. This is not the same as first doing the load and then only afterwards doing the store! How to represent the order in the SDAG? The SDAG is not a linear sequence of

I'm doing the delay slot optimization for MIPS and I've noticed that two other ports that are doing this have to work around a problem in the instruction abstraction. Would be nice to fix this and not propagate the hack. The basic problem is that on a call, you want to get the set of explicit and implicit operands but NOT the variable operands. There is no way do this without

Hi everyone, It says in document 'The LLVM Target-Independent Code Generator ': "SelectionDAGs contain two different kinds of values: those that represent data flow and those that represent control flow dependencies. Data values are simple edges with an integer or floating point value type. Control edges are represented as "chain" edges which are of type MVT::Other. These

Hi, I have committed the patch now (svn id 228686). Regarding the commenting you requested, I attach a patch. Feel free to make changes. I found it difficult to explain what the code does in isolated places, and thus kept my commenting quite short. This makes me feel like the code needs a bit of refactorization to make it more simple and understandable. Looking at the possibility of